Altera Arria V Hard IP for PCI Express - Manual (Page 154)

7–56 Chapter 7: IP Core Interfaces
Test Signals
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
lane_act[3:0] O
Lane Active Mode: This signal indicates the number of lanes that
configured during link training. The following encodings are defined:
■ 4’b0001: 1 lane
■ 4’b0010: 2 lanes
■ 4’b0100: 4 lanes
■ 4’b1000: 8 lanes
Notes to Table 7–27 :
(1) All signals are per lane.
(2) Refer to “PIPE Interface Signals” on page 7–51 for definitions of the PIPE interface signals.
Table 7–27. Test Interface Signals (1) , (2)
Signal I/O Description