Altera Arria V Hard IP for PCI Express - Manual (Page 118)

7–20 Chapter 7: IP Core Interfaces
Arria V Hard IP for PCI Express
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Data Alignment and Timing for the 128-Bit Avalon-ST TX Interface
Figure 7–22 shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs
for a three dword header with qword aligned addresses.
Figure 7–23 shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs
for a 3 dword header with non-qword aligned addresses. It also shows tx_st_err
assertion.
Figure 7–22. 128-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with Qword Aligned Address
Data3
Header2 Data 2
Header1 Data1 Data(n)
Header0 Data0 Data(n-1)
coreclkout
tx_st_valid
tx_st_data[127:96]
tx_st_data[95:64]
tx_st_data[63:32]
tx_st_data[31:0]
tx_st_sop
tx_st_eop
tx_st_empty
Figure 7–23. 128-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with non-Qword Aligned Address
coreclkout
tx_st_valid
tx_st_data[127:96]
tx_st_data[95:64]
tx_st_data[63:32]
tx_st_data[31:0]
tx_st_sop
tx_st_err
tx_st_eop
tx_st_empty
Data0 Data 4
Header 2 Data 3
Header 1 Data 2 Data (n)
Header 0 Data 1 Data (n-1)