Altera Arria V Hard IP for PCI Express - Manual (Page 176)

8–22 Chapter 8: Register Descriptions
Correspondence between Configuration Space Registers and the PCIe Spec 2.1
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
The Avalon-MM-to-PCI Express Mailbox registers are writable at the addresses
shown in Table 8–37 . When the Avalon-MM processor writes to one of these registers
the corresponding bit in the PCI Express Interrupt Status register is set to 1.
The PCI Express-to-Avalon-MM Mailbox registers are read-only at the addresses
shown in Table 8–38 . The Avalon-MM processor reads these registers when the
corresponding bit in the PCI Express to Avalon-MM Interrupt Status register is set
to 1.
Correspondence between Configuration Space Registers and the PCIe
Spec 2.1
Table 8–39 provides a comprehensive correspondence between the Configuration
Space registers and their descriptions in the PCI Express Base Specification 2.1.
Table 8–37. Avalon-MM-to-PCI Express Mailbox Registers 0x3A00–0x3A1F
Address Name Access Description
0x3A00 A2P_MAILBOX0 RW Avalon-MM-to-PCI Express mailbox 0
0x3A04 A2P_MAILBOX1 RW Avalon-MM-to-PCI Express mailbox 1
0x3A08 A2P _MAILBOX2 RW Avalon-MM-to-PCI Express mailbox 2
0x3A0C A2P _MAILBOX3 RW Avalon-MM-to-PCI Express mailbox 3
0x3A10 A2P _MAILBOX4 RW Avalon-MM-to-PCI Express mailbox 4
0x3A14 A2P _MAILBOX5 RW Avalon-MM-to-PCI Express mailbox 5
0x3A18 A2P _MAILBOX6 RW Avalon-MM-to-PCI Express mailbox 6
0x3A1C A2P_MAILBOX7 RW Avalon-MM-to-PCI Express mailbox 7
Table 8–38. PCI Express-to-Avalon-MM Mailbox Registers 0x3B00–0x3B1F
Address Name
Access
Mode
Description
0x3B00 P2A_MAILBOX0 RO PCI Express-to-Avalon-MM mailbox 0.
0x3B04 P2A_MAILBOX1 RO PCI Express-to-Avalon-MM mailbox 1
0x3B08 P2A_MAILBOX2 RO PCI Express-to-Avalon-MM mailbox 2
0x3B0C P2A_MAILBOX3 RO PCI Express-to-Avalon-MM mailbox 3
0x3B10 P2A_MAILBOX4 RO PCI Express-to-Avalon-MM mailbox 4
0x3B14 P2A_MAILBOX5 RO PCI Express-to-Avalon-MM mailbox 5
0x3B18 P2A_MAILBOX6 RO PCI Express-to-Avalon-MM mailbox 6
0x3B1C P2A_MAILBOX7 RO PCI Express-to-Avalon-MM mailbox 7
Table 8–39. Correspondence Configuration Space Registers and PCIe Base Specification Rev. 2.1 (Part 1 of 4)
Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification
Table 6-1. Common Configuration Space Header
0x000:0x03C PCI Header Type 0 Configuration Registers Type 0 Configuration Space Header
0x000:0x03C PCI Header Type 1 Configuration Registers Type 1 Configuration Space Header
0x040:0x04C Reserved