Altera Arria V Hard IP for PCI Express - Manual (Page 232)

17–10 Chapter 17: Testbench and Design Example
Chaining DMA Design Examples
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Chaining DMA Control and Status Registers
The software application programs the chaining DMA control register located in the
Endpoint application.
Table 17–2 describes the control registers which consists of four
dwords for the DMA write and four dwords for the DMA read. The DMA control
registers are read/write.
Table 17–3 describes the control fields of the of the DMA read and DMA write control
registers.
32-bit BAR4
32-bit BAR5
64-bit BAR5:4 Maps to 32 KByte target memory block. Use the rc_slave module to bypass the chaining DMA.
Expansion ROM BAR Not implemented by design example; behavior is unpredictable.
I/O Space BAR (any) Not implemented by design example; behavior is unpredictable.
Table 17–1. Design Example BAR Map
Table 17–2. Chaining DMA Control Register Definitions (1)
Addr
(2)
Register Name 3124 2316 150
0x0 DMA Wr Cntl DW0 Control Field (refer to Table 17–3 ) Number of descriptors in descriptor table
0x4 DMA Wr Cntl DW1 Base Address of the Write Descriptor Table (BDT) in the RC Memory–Upper DWORD
0x8 DMA Wr Cntl DW2 Base Address of the Write Descriptor Table (BDT) in the RC Memory–Lower DWORD
0xC DMA Wr Cntl DW3 Reserved RCLAST–Idx of last descriptor to process
0x10 DMA Rd Cntl DW0 Control Field (refer to Table 17–3 ) Number of descriptors in descriptor table
0x14 DMA Rd Cntl DW1 Base Address of the Read Descriptor Table (BDT) in the RC Memory–Upper DWORD
0x18 DMA Rd Cntl DW2 Base Address of the Read Descriptor Table (BDT) in the RC Memory–Lower DWORD
0x1C DMA Rd Cntl DW3 Reserved RCLAST–Idx of the last descriptor to process
Note to Table 17–2 :
(1) Refer to Figure 17–2 on page 17–6 for a block diagram of the chaining DMA design example that shows these registers.
(2) This is the Endpoint byte address offset from BAR2 or BAR3.
Table 17–3. Bit Definitions for the Control Field in the DMA Write Control Register and DMA Read Control Register
Bit Field Description
16 Reserved —
17 MSI_ENA
Enables interrupts of all descriptors. When 1, the Endpoint DMA module issues an
interrupt using MSI to the RC when each descriptor is completed. Your software
application or BFM driver can use this interrupt to monitor the DMA transfer status.
18 EPLAST_ENA
Enables the Endpoint DMA module to write the number of each descriptor back to
the EPLAST field in the descriptor table.
Table 17–7 describes the descriptor table.
[24:20] MSI Number
When your RC reads the MSI capabilities of the Endpoint, these register bits map
to the back-end MSI signals
app_msi_num [4:0]. If there is more than one MSI, the
default mapping if all the MSIs are available, is:
■ MSI 0 = Read
■ MSI 1 = Write