Link, Slot, Link –6 slot –6 – Altera Arria V Hard IP for PCI Express User Manual
Page 58
4–6
Chapter 4: Parameter Settings for the Arria V Hard IP for PCI Express
Port Functions
Arria V Hard IP for PCI Express
December 2013
Altera Corporation
User Guide
Link
Table 4–4
describes the Link Capabilities parameters.
Slot
Table 4–12
describes the Slot Capabilities parameters.
Table 4–4. Link Capabilities
Parameter
Value
Description
Link port number
0x01
(default
value)
Sets the read-only value of the port number field in the
Link Capabilities
register. This is an 8-bit field which you can specify.
Slot clock
configuration
On/Off
When On, indicates that the Endpoint or Root Port uses the same physical reference
clock that the system provides on the connector. When Off, the IP core uses an
independent clock regardless of the presence of a reference clock on the connector.
Table 4–5. Slot Capabilities
Parameter
Value
Description
Use Slot register
On/Off
The slot capability is required for Root Ports if a slot is implemented on the port. Slot
status is recorded in the
PCI
Express
Capabilities
Register
. This parameter is
only valid for Root Port variants.
Defines the characteristics of the slot. You turn this option on by selecting. The
various bits of the Slot Capability register have the following definitions:
Slot power scale
0–3
Specifies the scale used for the Slot power limit. The following coefficients are
defined:
■
0 = 1.0x
■
1 = 0.1x
■
2 = 0.01x
■
3 = 0.001x
The default value prior to hardware and firmware initialization is b’0 or 1.0x. Writes
to this register also cause the port to send the
Set_Slot_Power_Limit
Message.
Refer to Section 6.9 of
for more
information.
31
19 18 17 16 15 14
7 6
5
Physical Slot Number
No Command Completed Support
Electromechanical Interlock Present
Slot Power Limit Scale
Slot Power Limit Value
Hot-Plug Capable
Hot-Plug Surprise
Power Indicator Present
Attention Indicator Present
MRL Sensor Present
Power Controller Present
Attention Button Present
0
4
3
2
1