Altera Arria V Hard IP for PCI Express - Manual (Page 31)

Chapter 2: Getting Started with the Arria Hard IP for PCI Express 2–15
Compiling the Design in the Qsys Design Flow
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Compiling the Design in the MegaWizard Plug-In Manager Design Flow
Before compiling the complete example design in the Quartus II software, you must
add the example design files that you generated in Qsys to your Quartus II project.
The Quartus II IP File (.qip) lists all files necessary to compile the project.
Follow these steps to add the Quartus II IP File (.qip) to the project:
1. On the Project menu, select Add/Remove Files in Project.
2. Click the browse button next the File name box and browse to the
gen1_x4_example_design/altera_pcie_sv_hip_ast/pcie_de_gen1_x4_ast64/
synthesis/
directory.
3. In the Files of type list, Click pcie_de_ge1_x4_ast64.qip and then click Open.
4. On the Add Files page, click Add, then click OK.
5. Add the Synopsys Design Constraints (SDC) shown in the following example, to
the top-level design file for your Quartus II project.
6. On the Processing menu, select Start Compilation.
Compiling the Design in the Qsys Design Flow
To compile the Qsys design example in the Quartus II software, you must create a
Quartus II project and add your Qsys files to that project.
Complete the following steps to create your Quartus II project:
1. From the Windows Start Menu, choose Programs > Altera > Quartus II 13.1 to run
the Quartus II software.
Example 2–2. Synopsys Design Constraint
create_clock -period “100 MHz” -name {refclk_pci_express} {*refclk_*}
derive_pll_clocks
derive_clock_uncertainty
######################################################################
# PHY IP reconfig controller constraints
# Set reconfig_xcvr clock
# Modify to match the actual clock pin name
# used for this clock, and also changed to have the correct period set
create_clock -period "125 MHz" -name {reconfig_xcvr_clk}
{*reconfig_xcvr_clk*}
######################################################################
# HIP Soft reset controller SDC constraints
set_false_path -to [get_registers
*altpcie_rs_serdes|fifo_err_sync_r[0]]
set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to
[get_registers *altpcie_rs_serdes|*]
# Hard IP testin pins SDC constraints
set_false_path -from [get_pins -compatibilitly_mode *hip_ctrl*]