Altera Arria V Hard IP for PCI Express - Manual (Page 281)

Chapter : A–3
TLP Packet Format with Data Payload
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
TLP Packet Format with Data Payload
Table A–10 through Table A–16 show the content for TLPs with a data payload.
Table A–10. Memory Write Request, 32-Bit Addressing
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 1 0 0 0 0 0 0 0 TC 0 0 0 0 TD EP Attr AT Length
Byte 4 Requester ID Tag Last BE First BE
Byte 8 Address[31:2] 0 0
Byte 12 Reserved
Table A–11. Memory Write Request, 64-Bit Addressing
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 1 1 0 0 0 0 0 0 TC 0 0 0 0 TD EP Attr AT Length
Byte 4 Requester ID Tag Last BE First BE
Byte 8 Address[63:32]
Byte 12 Address[31:2] 0 0
Table A–12. Configuration Write Request Root Port (Type 1)
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 R 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 TD EP 0 0 AT 0 0 0 0 0 0 0 0 0 1
Byte 4 Requester ID Tag 0 0 0 0 First BE
Byte 8 Bus Number Device No 0 0 0 0 Ext Reg Register No 0 0
Byte 12 Reserved
Table A–13. I/O Write Request
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 TD EP 0 0 AT 0 0 0 0 0 0 0 0 0 1
Byte 4 Requester ID Tag 0 0 0 0 First BE
Byte 8 Address[31:2] 0 0
Byte 12 Reserved
Table A–14. Completion with Data
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 1 0 0 1 0 1 0 0 TC 0 0 0 0 TD EP Attr AT Length
Byte 4 Completer ID Status B Byte Count
Byte 8 Requester ID Tag 0 Lower Address
Byte 12 Reserved