Altera Arria V Hard IP for PCI Express - Manual (Page 207)

December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
13. Flow Control
Throughput analysis requires that you understand the Flow Control Loop, shown in
“Flow Control Update Loop” on page 13–2 . This chapter discusses the Flow Control
Loop and strategies to improve throughput. It covers the following topics:
■ Throughput of Posted Writes
■ Throughput of Non-Posted Reads
Throughput of Posted Writes
The throughput of posted writes is limited primarily by the Flow Control Update loop
shown in
Figure 13–1 . If the write requester sources the data as quickly as possible,
and the completer consumes the data as quickly as possible, then the Flow Control
Update loop may be the biggest determining factor in write throughput, after the
actual bandwidth of the link.
Figure 13–1 shows the main components of the Flow Control Update loop with two
communicating PCI Express ports:
■ Write Requester
■ Write Completer
As the PCI Express Base Specification 2.1 describes, each transmitter, the write requester
in this case, maintains a Credit Limit Register and a Credits Consumed Register .
The Credit Limit Register is the sum of all credits issued by the receiver, the write
completer in this case. The Credit Limit Register is initialized during the flow
control initialization phase of link initialization and then updated during operation by
Flow Control (FC) Update DLLPs. The
Credits Consumed Register is the sum of all
credits consumed by packets transmitted. Separate Credit Limit and Credits
Consumed Registers exist for each of the six types of Flow Control:
■ Posted Headers
■ Posted Data
■ Non-Posted Headers
■ Non-Posted Data
■ Completion Headers
■ Completion Data
December 2013
UG-01110-1.5