Datasheet, Features, Chapter 1. datasheet – Altera Arria V Hard IP for PCI Express User Manual

Page 9: Features –1

December 2013

Altera Corporation

Arria V Hard IP for PCI Express

User Guide

1. Datasheet

This document describes the Altera

Arria

V Hard IP for PCI Express

. PCI Express

is a high-performance interconnect protocol for use in a variety of applications
including network adapters, storage area networks, embedded controllers, graphic
accelerator boards, and audio-video products. The PCI Express protocol is software
backwards-compatible with the earlier PCI and PCI-X protocols, but is significantly
different from its predecessors. It is a packet-based, serial, point-to-point interconnect
between two devices. The performance is scalable based on the number of lanes and
the generation that is implemented. Altera offers a configurable hard IP block in Arria

V devices for both Endpoints and Root Ports that complies with the

PCI Express Base

Specification 2.1

. Using a configurable hard IP block, rather than programmable logic,

saves significant FPGA resources. The hard IP block is available in ×1, ×2, ×4, and ×8
configurations.

Table 1–1

shows the aggregate bandwidth of a PCI Express link for the

available configurations. The protocol specifies 2.5 giga-transfers per second for Gen1
and 5 giga-transfers per second for Gen2.

Table 1–1

provides bandwidths for a single

transmit (TX) or receive (RX) channel, so that the numbers double for duplex
operation. Because the PCI Express protocol uses 8B/10B encoding, there is a 20%
overhead which is included in the figures in

Table 1–1

Refer to the

PCI Express High Performance Reference Design

for more information about

calculating bandwidth for the hard IP implementation of PCI Express in many Altera
FPGAs.

Features

The Arria V Hard IP for PCI Express IP supports the following key features:

■

Complete protocol stack including the Transaction, Data Link, and Physical Layers
is hardened in the device.

■

Multi-function support for up to eight Endpoint functions.

■

Support for ×1, ×2, ×4, and ×8 Gen1 and Gen2 configurations for Root Ports and
Endpoints.

■

Dedicated 6 KByte receive buffer

■

Dedicated hard reset controller

■

MegaWizard Plug-In Manager and Qsys support using the Avalon

Streaming

(Avalon-ST) with a 64- or 128-bit interface to the Application Layer.

Table 1–1. PCI Express Throughput

Link Width

×1

×2

×4

×8

PCI Express Gen1 Gbps (2.5 Gbps)

2.5

PCI Express Gen2 Gbps (5.0 Gbps)

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December 2013
UG-01110-1.5