Altera Arria V Hard IP for PCI Express - Manual (Page 41)

Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express 3–7
Adding the Remaining Components to the Qsys System
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
7. Click Finish.
8. The On-chip memory component is added to your Qsys system.
9. On the File menu, click Save and type the file name ep_g1x4.qsys . You should
save your work frequently as you complete the steps in this walkthrough.
10. On the Component Library tab, type the following text string in the search box:
recon
r
Qsys filters the component library and shows all components matching the text
string you entered.
11. Click Transceiver Reconfiguration Controller and then click +Add. Specify the
parameters listed in Table 3–10 .
1 Originally, you set the Number of reconfiguration interfaces to 5 . Although you
must initially create a separate logical reconfiguration interface for each channel and
TX PLL in your design, when the Quartus II software compiles your design, it merges
logical channels. After compilation, the design has two reconfiguration interfaces, one
for the TX PLL and one for the channels; however, the number of logical channels is
still five.
Enable In-System Memory Content Editor feature D Turn off this option
Instance ID Not required
Table 3–10. Transceiver Reconfiguration Controller Parameters
Parameter Value
Device family Arria
Interface Bundles
Number of reconfiguration interfaces 5
Optional interface grouping Leave this entry blank
Transceiver Calibration Functions
Enable offset cancellation Leave this option on
Enable PLL calibration Leave this option on
Create optional calibration status ports Leave this option off
Analog Features
Enable Analog controls Turn this option on
Enable EyeQ block Leave this option off
Enable decision feedback equalizer (DFE) block Leave this option off
Enable AEQ block Leave this option off
Reconfiguration Features
Enable channel/PLL reconfiguration Leave this option off
Enable PLL reconfiguration support block Leave this option off
Table 3–9. On-Chip Memory Parameters (Part 2 of 2)
Parameter Value