Altera Arria V Hard IP for PCI Express - Manual (Page 229)

Chapter 17: Testbench and Design Example 17–7
Chaining DMA Design Examples
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
The chaining DMA design example hierarchy consists of these components:
■ A DMA read and a DMA write module
■ An on-chip Endpoint memory (Avalon-MM slave) which uses two Avalon-MM
interfaces for each engine
■ The RC slave module is used primarily for downstream transactions which target
the Endpoint on-chip buffer memory. These target memory transactions bypass
the DMA engines. In addition, the RC slave module monitors performance and
acknowledges incoming message TLPs.
Each DMA module consists of these components:
■ Control register module—The RC programs the control register (four dwords)
to start the DMA.
■ Descriptor module—The DMA engine fetches four dword descriptors from
BFM shared memory which hosts the chaining DMA descriptor table.
■ Requester module—For a given descriptor, the DMA engine performs the
memory transfer between Endpoint memory and the BFM shared memory.