Altera Arria V Hard IP for PCI Express - Manual (Page 59)

Chapter 4: Parameter Settings for the Arria V Hard IP for PCI Express 4–7
Port Functions
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Power Management
Table 4–6 describes the Power Management parameters.
Parameters Defined Separately for All Port Functions
You can specify parameter settings for up to eight functions. Each function has
separate settings for the following parameters:
■ Base Address Registers for Function
■ Base and Limit Registers for Root Port Func
■ Device ID Registers for Function
■ PCI Express/PCI Capabilities for Func
Slot power limit 0–255
In combination with the Slot power scale value, specifies the upper limit in watts on
power supplied by the slot. Refer to Section 7.8.9 of the
PCI Express Base Specification
Revision 2.1 for more information.
Slot number 0-8191 Specifies the slot number.
Table 4–5. Slot Capabilities 0x094
Parameter Value Description
Table 4–6. Power Management Parameters
Parameter Value Description
Endpoint L0s
acceptable latency
< 64 ns – > No limit
This design parameter specifies the maximum acceptable latency that the
device can tolerate to exit the L0s state for any links between the device and
the root complex. It sets the read-only value of the Endpoint L0s acceptable
latency field of the
Device Capabilities register ( 0x084 ).
The Arria V Hard IP for PCI Express does not support the L0s or L1 states.
However, in a switched system there may be links connected to switches
that have L0s and L1 enabled. This parameter is set to allow system
configuration software to read the acceptable latencies for all devices in the
system and the exit latencies for each link to determine which links can
enable Active State Power Management (ASPM). This setting is disabled for
Root Ports.
The default value of this parameter is 64 ns. This is the safest setting for
most designs.
Endpoint L1
acceptable latency
< 1 µs to > No limit
This value indicates the acceptable latency that an Endpoint can withstand
in the transition from the L1 to L0 state. It is an indirect measure of the
Endpoint’s internal buffering. It sets the read-only value of the Endpoint L1
acceptable latency field of the
Device Capabilities register.
The Arria V Hard IP for PCI Express does not support the L0s or L1 states.
However, in a switched system there may be links connected to switches
that have L0s and L1 enabled. This parameter is set to allow system
configuration software to read the acceptable latencies for all devices in the
system and the exit latencies for each link to determine which links can
enable Active State Power Management (ASPM). This setting is disabled for
Root Ports.
The default value of this parameter is 1 .µs. This is the safest setting for
most designs.