Altera Arria V Hard IP for PCI Express - Manual (Page 49)

Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express 3–15
Simulating the Single DWord Design
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Simulating the Single DWord Design
You can use the same testbench to simulate the Completer-Only single dword IP core
by changing the settings in the driver file. Complete the following steps for the
Verilog HDL design example:
1. In a terminal window, change to the //testbench/
_tb/simulation/submodules directory.
2. Open altpcietb_bfm_driver_avmm.v file your text editor.
3. To enable target memory tests and specify the completer-only single dword
variant, specify the following parameters:
■ parameter RUN_TGT_MEM_TST = 1;
■ parameter RUN_DMA_MEM_TST = 0;
■ parameter AVALON_MM_LITE = 1;
4. Change to the < project_dir>//testbench/mentor directory.
5. Start the ModelSim simulator.
6. To run the simulation, type the following commands in a terminal window:
a. do msim_setup.tcl
r
b. ld_debug
r (The -debug suffix stops optimizations, improving visibility in the
ModelSim waveforms.)
c. run 140000 ns
r
Understanding Channel Placement Guidelines
Arria transceivers are organized in banks of three and six channels for 6-Gbps
operation and in banks of two channels for 10-Gbps operation. The transceiver bank
boundaries are important for clocking resources, bonding channels, and fitting. Refer
to
“Channel Placement Using CMU PLL” on page 7–50 and “Channel Placement for
×8 Variants” on page 7–49 for information about channel placement for ×1, ×4, and ×8
variants.
f For more information about Arria transceivers refer to the “Transceiver Banks”
section in the
Transceiver Architecture in Arria V Devices .
Example 3–1. Transcript from ModelSim Simulation of Gen1 x4 Endpoint (continued)
# INFO: 54368 ns Setup BAR = 2
# INFO: 54368 ns Length = 000512, Start Offset = 000000
# INFO: 60609 ns Interrupt Monitor: Interrupt INTA Asserted
# INFO: 60609 ns Clear Interrupt INTA
# INFO: 62225 ns Interrupt Monitor: Interrupt INTA Deasserted
# INFO: 69361 ns MSI recieved!
# INFO: 69361 ns DMA Read and Write compared okay!
# SUCCESS: Simulation stopped due to successful completion!
# Break at ./..//ep_g1x4_tb/simulation/submodules//altpcietb_bfm_log.v line 78