Altera Arria V Hard IP for PCI Express - Manual (Page 35)

December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
3. Getting Started with the Avalon-MM
Arria Hard IP for PCI Express
This Qsys design example provides detailed step-by-step instructions to generate a
Qsys system. When you install the Quartus II software you also install the IP Library.
This installation includes design examples for the Avalon-MM Arria Hard IP for PCI
Express in the /ip/altera/altera_pcie/altera_pcie_av_hip_avmm/
example_designs/
directory.
The design examples contain the following components:
■ Avalon-MM Arria Hard IP for PCI Express ×4 IP core
■ On-Chip memory
■ DMA controller
■ Transceiver Reconfiguration Controller
In the Qsys design flow you select the Avalon-MM Arria Hard IP for PCI Express as a
component. This component supports PCI Express ×1, ×4, or ×8 Endpoint
applications with bridging logic to convert PCI Express packets to Avalon-MM
transactions and vice versa. The design example included in this chapter illustrates
the use of an Endpoint with an embedded transceiver.
Figure 3–1 provides a high-level block diagram of the design example included in this
release.
Figure 3–1. Qsys Generated Endpoint
Transaction,
Data Link,
and PHY
Layers
On-Chip
Memory
DMA
Qsys System Design for PCI Express
PCI Express
Link
PCI
Express
Avalon-MM
Bridge
Interconnect
Avalon-MM Hard IP for PCI Express
Transceiver
Reconfiguration
Controller
December 2013
UG-01110-1.5