Altera Arria V Hard IP for PCI Express - Manual (Page 226)

17–4 Chapter 17: Testbench and Design Example
Chaining DMA Design Examples
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
1 One parameter, serial_sim_hwtcl , in the altprice_tbed_sv_hwtcl.v file, controls
whether the testbench simulates in PIPE mode or serial mode. When is set to 0, the
simulation runs in PIPE mode; otherwise, it runs in serial mode.
Chaining DMA Design Examples
This design examples shows how to create a chaining DMA Native Endpoint which
supports simultaneous DMA read and write transactions. The write DMA module
implements write operations from the Endpoint memory to the root complex (RC)
memory. The read DMA implements read operations from the RC memory to the
Endpoint memory.
When operating on a hardware platform, the DMA is typically controlled by a
software application running on the root complex processor. In simulation, the
generated testbench, along with this design example, provides a BFM driver module
in Verilog HDL that controls the DMA operations. Because the example relies on no
other hardware interface than the PCI Express link, you can use the design example
for the initial hardware validation of your system.
The design example includes the following two main components:
■ The Root Port variation
■ An Application Layer design example
The end point or Root Port variant is generated in the language (Verilog HDL or
VHDL) that you selected for the variation file. The testbench files are only generated
in Verilog HDL in the current release. If you choose to use VHDL for your variant, you
must have a mixed-language simulator to run this testbench.
1 The chaining DMA design example requires setting BAR 2 or BAR 3 to a minimum of
256 bytes. To run the DMA tests using MSI, you must set the Number of MSI
messages requested
parameter under the PCI Express/PCI Capabilities page to at
least 2.
The chaining DMA design example uses an architecture capable of transferring a
large amount of fragmented memory without accessing the DMA registers for every
memory block. For each block of memory to be transferred, the chaining DMA design
example uses a descriptor table containing the following information:
■ Length of the transfer
■ Address of the source
■ Address of the destination
■ Control bits to set the handshaking behavior between the software application or
BFM driver and the chaining DMA module
1 The chaining DMA design example only supports dword-aligned accesses. The
chaining DMA design example does not support ECRC forwarding for Arria V.