Altera Arria V Hard IP for PCI Express User Manual
Page 130
7–32
Chapter 7: IP Core Interfaces
Arria V Hard IP for PCI Express
Arria V Hard IP for PCI Express
December 2013
Altera Corporation
User Guide
Table 7–12
describes the bits of the
tl_cfg_sts
bus for all eight functions. Refer to
for the layout of the configuration control and status
information.
Table 7–12. Mapping Between tl_cfg_sts and Configuration Space Registers (Part 1 of 2)
tl_cfg_sts
Configuration Space Register
Description
[62:59] Func1
[72:69] Func2
[82:79] Func3
[92:89] Func4
[102:99] Func5
[112:109] Func6
[122:119] Func7
Device Status Reg[3:0]
Records the following errors:
■
Bit 3: unsupported request
■
Bit 2: fatal error
■
Bit 1: non-fatal error
■
Bit 0: correctable error
[58:54] Func1
[68:64] Func2
[78:74] Func3
[88:84] Func4
[98:94] Func5
[108:104] Func6
[118:114] Func7
Link Status Reg[15:11]
Link status bits as follows:
■
Bit 15: link autonomous bandwidth status
■
Bit 14: link bandwidth management status
■
Bit 13: Data Link Layer link active
■
Bit 12: slot clock configuration
■
Bit 11: link training
[53] Func1
[63] Func2
[73] Func3
[83] Func4
[93] Func5
[103] Func6
[113] Func7
Secondary Status Register[8]
6th primary command status error bit. Master data parity error.
[52:49]
Device Status Register[3:0]
Records the following errors:
■
Bit 3: unsupported request detected
■
Bit 2: fatal error detected
■
Bit 1: non-fatal error detected
■
Bit 0: correctable error detected
[48]
Slot Status Register[8]
Data Link Layer state changed
[47]
Slot Status Register[4]
Command completed. (The hot plug controller completed a
command.)
[46:31]
Link Status Register[15:0]
Records the following link status information:
■
Bit 15: link autonomous bandwidth status
■
Bit 14: link bandwidth management status
■
Bit 13: Data Link Layer link active
■
Bit 12: Slot clock configuration
■
Bit 11: Link Training
■
Bit 10: Undefined
■
Bits[9:4]: Negotiated Link Width
■
Bits[3:0] Link Speed
[30]
Link Status 2 Register[0]
Current de-emphasis level.