Altera Arria V Hard IP for PCI Express User Manual
Page 147
Chapter 7: IP Core Interfaces
7–49
Physical Layer Interface Signals
December 2013
Altera Corporation
Arria V Hard IP for PCI Express
User Guide
Channel utilization for ×1, ×2, ×4, and ×8 variants is as follows:
f
For more comprehensive information about Arria transceivers refer to the
“Transceiver Banks” section in the
The following figures show the channel utilization for Gen1 and Gen2 variants using
the CMU PLL. The ×8 variant is only available for Gen1.
Table 7–1. Channel Utilization for Data and Clock Routing
Variant
Data
CMU Clock
×1, 1 instance
Channel 1 of GXB_L0
Channel 0 of GXB_L0
×1, 2 instances
Channel 1 of GXB_L0
Channel 1 of GXB_R0
Channel 0 of GXB_L0
Channel 0 of GXB_R0
×2, i instance
Channel 1-2 of GXB_L0
Channel 4 of GXB_L0
×2, 2 instances
Channel 1-2 of GXB_L0
Channel 1-2 of GXB_R0
Channel 4 of GXB_L0
Channel 4 of GXB_R0
×4, i instance
Channels 0-3 of GXB_L0
Channel 4 of GXB_L0
×4, 2 instances
Channels 0-3 of GXB_L0
Channels 0-3 of GXB_R0
Channel 4 of GXB_L0
Channel 4 of GXB_R0
×8, 1 instance
Channels, 0-3 and 5 of GXB_L0
and channels 0-2 of GXB_L1
Channel 4 of GXB_L0
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)