Altera Arria V Hard IP for PCI Express - Manual (Page 108)

7–10 Chapter 7: IP Core Interfaces
Arria V Hard IP for PCI Express
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Figure 7–7 shows the mapping of Avalon-ST RX packet to PCI Express TLPs for TLPs
for a four dword header with non-qword addresses with a 64-bit bus. Note that the
address of the first dword is 0x4. The address of the first enabled byte is 0x6. This
example shows one valid word in the first dword, as indicated by the
rx_st_be signal.
Figure 7–8 illustrates the timing of the RX interface when the Application Layer
backpressures the Arria V Hard IP for PCI Express by deasserting rx_st_ready . The
rx_st_valid signal must deassert within three cycles after rx_st_ready is deasserted.
In this example, rx_st_valid is deasserted in the next cycle. rx_st_data is held until
the Application Layer is able to accept it.
Figure 7–7. 64-Bit Avalon-ST rx_st_data Cycle Definitions for 4-Dword Header TLP with Non-Qword Address (1)
Note to Figure 7–7 :
(1) rx_st_be[7:4] corresponds to rx_st_data[63:32] . rx_st_be[3:0] corresponds to rx_st_data[31:0] .
coreclkout
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_bar[7:0]
rx_st_be[7:4]
rx_st_be[3:0]
header1 header3 data0 data2
header0 header2 data1
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Figure 7–8. 64-Bit Application Layer Backpressures Transaction Layer for RX Transactions
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_bardec[7:0]
rx_st_be[7:4]
rx_st_be[3:0]
header0 header2 data1
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C F
F