Altera Arria V Hard IP for PCI Express - Manual (Page 156)

8–2 Chapter 8: Register Descriptions
Configuration Space Register Content
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Table 8–2 describes the Type 0 Configuration settings.
1 In the following tables, the names of fields that are defined by parameters in the
parameter editor are links to the description of that parameter. These links appear as
green text.
Table 8–3 describes the Type 1 Configuration settings.
Table 8–2. PCI Type 0 Configuration Space Header (Endpoints), Rev2.1
Byte Offset 31:24 23:16 15:8 7:0
0x000 Device ID Vendor ID
0x004 Status Command
0x008 Class code Revision ID
0x00C 0x00
Header Type
( Port type )
0x00 Cache Line Size
0x010 Func0–Func7 BARs and Expansion ROM
0x014 Func0–Func7 BARs and Expansion ROM
0x018 Func0–Func7 BARs and Expansion ROM
0x01C Func0–Func7 BARs and Expansion ROM
0x020 Func0–Func7 BARs and Expansion ROM
0x024 Func0–Func7 BARs and Expansion ROM
0x028 Reserved
0x02C Subsystem Device ID Subsystem Vendor ID
0x030 Expansion ROM base address
0x034 Reserved Capabilities Pointer
0x038 Reserved
0x03C 0x00 0x00 Interrupt Pin Interrupt Line
Note to Table 8–2 :
(1) Refer to Table 8–39 on page 8–22 for a comprehensive list of correspondences between the Configuration Space registers and the PCI Express
Base Specification 2.1 .
Table 8–3. PCI Type 1 Configuration Space Header (Root Ports) (Part 1 of 2)
Byte Offset 31:24 23:16 15:8 7:0
0x0000 Device ID Vendor ID
0x004 Status Command
0x008 Class code Revision ID
0x00C BIST Header Type
Primary Latency
Timer
Cache Line Size
0x010 Reserved
0x014 Reserved
0x018
Secondary Latency
Timer
Subordinate Bus
Number
Secondary Bus
Number
Primary Bus Number
0x01C Secondary Status I/O Limit I/O Base
0x020 Memory Limit Memory Base