Device id registers for function Page 61
Page 61
Chapter 4: Parameter Settings for the Arria V Hard IP for PCI Express
4–9
Port Functions
December 2013
Altera Corporation
Arria V Hard IP for PCI Express
User Guide
describes the Base and Limit
registers parameters.
Device ID Registers for Function
Table 4–9
lists the default values of the read-only Device ID registers. You can use the
parameter editor to change the values of these registers. At run time, you can change
the values of these registers using the reconfiguration block signals. For more
information, refer to
“R**Hard IP Reconfiguration Interface ###if_hip_reconfig###” on
page 8–52
.
Table 4–8. Base and Limit Registers
Parameter
Value
Description
Input/Output
Disable
16-bit I/O addressing
32-bit I/O addressing
Specifies the address widths for the
IO base
and
IO limit
registers.
Prefetchable memory
Disable
32-bit memory addressing
64-bit memory addressing
Specifies the address widths for the
Prefetchable Memory
Base
register and
Prefetchable Memory Limit
register.
Table 4–9. Device ID Registers for Function
Register Name/
Offset Address
Range
Default
Value
Description
Vendor ID
16 bits
0x00000000
Sets the read-only value of the
Vendor ID
register. This parameter can
not be set to 0xFFFF per the PCI Express Specification.
Device ID
16 bits
0x00000001
Sets the read-only value of the
Device ID
register.
Revision ID
8 bits
0x00000001
Sets the read-only value of the
Revision ID
register.
Class code
24 bits
0x00000000
Sets the read-only value of the
Class Code
register.
Subsystem
Vendor ID
16 bits
0x00000000
Sets the read-only value of the
Subsystem Vendor ID
register. This
parameter cannot be set to 0xFFFF per the
This register is available only for Endpoint designs
which require the use of the Type 0 PCI Configuration register.
Subsystem
Device ID
16 bits
0x0000000
Sets the read-only value of the
Subsystem Device ID
register. This
register is only available for Endpoint designs, which require the use of
the Type 0 PCI Configuration Space.