Use the pipe interface for gen1 and gen2 variants, Reduce counter values for serial simulations – Altera Arria V Hard IP for PCI Express User Manual
Page 277

Chapter 18: Debugging
18–7
Setting Up Simulation
December 2013
Altera Corporation
Arria V Hard IP for PCI Express
User Guide
1. In the top-level testbench, which is
, change the module instantiation
parameter,
hip_ctrl_simu_mode_pipe
. to 1'b1 as shown:
pcie_de_gen1_x4_ast64 pcie_de_gen1_x4_ast64_inst
(.hip_ctrl_simu_mode_pipe ( 1'b1 )
,
2. In the top-level HDL module for the Hard IP which is work_dir>
/
, change
the module instantiation parameter,
enable_pipe32_sim_hwtcl
. to 1'b1 as shown:
altpcie_
Use the PIPE Interface for Gen1 and Gen2 Variants
Running the simulation in PIPE mode reduces simulation time and provides greater
visibility. PIPE simulation is available for Gen1 and Gen2 variants in the current
release.
Complete the following steps to simulate using the PIPE interface:
1. Change to your simulation directory,
2. Open
3. Search for the string,
serial_sim_hwtcl
. Set the value of this parameter to 0 if it is
1.
4. Save
Reduce Counter Values for Serial Simulations
You can accelerate simulation by reducing the value of counters whose default values
are set for hardware, not simulation.
Complete the following steps to reduce counter values for simulation:
1. Open
altpcie_tbed_sv_hwtcl.v
.
2. Search for the string,
test_in
.
3. To reduce the value of several counters, set
test_in[0] = 1
.
4. Save altpcie_tbed_sv_hwtcl.v.
Disable the Scrambler for Gen1 and Gen2 Simulations
The 128b/130b encoding scheme implemented by the scrambler applies a binary
polynomial to the data stream to ensure enough data transitions between 0 and 1 to
prevent clock drift. The data is decoded at the other end of the link by running the
inverse polynomial.
Complete the following steps to disable the scrambler:
1. Open
altpcie_tbed_sv_hwtcl.v
.
2. Search for the string,
test_in
.