Altera Arria V Hard IP for PCI Express - Manual (Page 196)

11–2 Chapter 11: Interrupts
Interrupts for Endpoints Using the Avalon-ST Application Interface
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Figure 11–1 illustrates the architecture of the MSI handler block.
Figure 11–2 illustrates a possible implementation of the MSI handler block with a per
vector enable bit. A global Application Layer interrupt enable can also be
implemented instead of this per vector MSI.
Figure 11–1. MSI Handler Block
Figure 11–2. Example Implementation of the MSI Handler Block
MSI Handler
Block
app_msi_req
app_msi_ack
app_msi_tc
app_msi_num
pex_msi_num
app_int_sts
cfg_msicsr[15:0]
app_int_en0
app_int_sts0
app_msi_req0
app_int_en1
app_int_sts1
app_msi_req1
app_int_sts
MSI
Arbitration
msi_enable & Master Enable
app_msi_req
app_msi_ack
Vector 1
Vector 0
R/W
R/W