Adding synopsis design constraints, Creating a quartus ii project – Altera Arria V Hard IP for PCI Express User Manual
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Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express
Adding Synopsis Design Constraints
Arria V Hard IP for PCI Express
December 2013
Altera Corporation
User Guide
Adding Synopsis Design Constraints
Before you can compile your design using the Quartus II software, you must add a
few Synopsys Design Constraints (SDC) to your project. Complete the following steps
to add these constraints:
1. Browse to
2. Add the constraints shown in
Example 3–2
to altera_pci_express.sdc.
1
Because altera_pci_express.sdc is overwritten each time you regenerate your design,
you should save a copy of this file in an additional directory that the Quartus II
software does not overwrite.
Creating a Quartus II Project
You can create a new Quartus II project with the New Project Wizard, which helps
you specify the working directory for the project, assign the project name, and
designate the name of the top-level design entity. To create a new project follow these
steps:
1. On the Quartus II File menu, click New, then New Quartus II Project, then OK.
2. Click Next in the New Project Wizard: Introduction (The introduction does not
appear if you previously turned it off.)
3. On the Directory, Name, Top-Level Entity page, enter the following information:
a. For What is the working directory for this project, browse to
b. For What is the name of this project, select ep_g1x4 from the synthesis
directory.
4. Click Next.
5. On the Add Files page, add
your Quartus II project. This file lists all necessary files for Quartus II compilation,
including the altera_pci_express.sdc that you just modified.
6. Click Next to display the Family & Device Settings page.
7. On the Device page, choose the following target device family and options:
a. In the Family list, select Arria V.
b. In the Devices list, select Arria V GX Extended Features.
c. In the Available devices list, select V5AGXFB3H6F35C6.
8. Click Next to close this page and display the EDA Tool Settings page.
Example 3–2. Synopsys Design Constraints
create_clock -period “100 MHz” -name {refclk_pci_express} {*refclk_*}
create_clock -period "125 MHz" -name {reconfig_xcvr_clk}
{*reconfig_xcvr_clk*}
derive_pll_clocks
derive_clock_uncertainty