Altera Arria V Hard IP for PCI Express - Manual (Page 247)

Chapter 17: Testbench and Design Example 17–25
Root Port BFM
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Besides the ebfm_cfg_rp_ep procedure inaltpcietb_bfm_driver_rp.v, routines to read
and write Endpoint Configuration Space registers directly are available in the Verilog
HDL include file. After the
ebfm_cfg_rp_ep procedure is run the PCI Express I/O and
Memory Spaces have the layout as described in the following three figures. The
memory space layout is dependent on the value of the addr_map_4GB_limit input
parameter. If addr_map_4GB_limit is 1 the resulting memory space map is shown in
Figure 17–5 .
Figure 17–5. Memory Space Layout—4 GByte Limit
Root Complex Shared
Memory
0x0000 0000
Configuration Scratch
Space
Used by BFM routines ,
not writable by user calls
or endpoint
0x001F FF80
BAR Table
Used by BFM routines ,
not writable by user calls
or endpoint
0x001F FFC0
Endpoint Non -
Prefetchable Memory
Space BARs
Assigned Smallest to
Largest
0x0020 0000
0xFFFF FFFF
Endpoint Memory Space
BARs
( Prefetchable 32 -bit and
64- bit )
Assigned Smallest to
Largest
Unused
Addr