Altera Arria V Hard IP for PCI Express - Manual (Page 282)

A–4 Chapter :
TLP Packet Format with Data Payload
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Table A–15. Completion Locked with Data
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 1 0 0 1 0 1 1 0 TC 0 0 0 0 TD EP Attr AT Length
Byte 4 Completer ID Status B Byte Count
Byte 8 Requester ID Tag 0 Lower Address
Byte 12 Reserved
Table A–16. Message with Data
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 1 1 1 0
r
2 r
1 r
0
0 TC 0 0 0 0 TD EP 0 0 AT Length
Byte 4 Requester ID Tag Message Code
Byte 8 Vendor defined or all zeros for Slot Power Limit
Byte 12 Vendor defined or all zeros for Slots Power Limit
Notes to Table A–16 :
(1) Not supported in Avalon-MM.