Intel PXA26X - Manual (Page 98)

3-32 Intel® PXA26x Processor Family Developer’s Manual
Clocks and Power Manager
Warning: Because GPIO[89:86] were previously dedicated pins, they only reflect their PGSR value if their
GPIO function is selected. Otherwise they drive their dedicated pin’s sleep state.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 3-16. PGSR0 Bit Definitions
0x40F0_0020 PGSR0 Clocks and Power Manager
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
3
1
SS
3
0
SS
2
9
SS
2
8
SS
2
7
SS
2
6
SS
2
5
SS
2
4
SS
2
3
SS
2
2
SS
2
1
SS
2
0
SS
1
9
SS
1
8
SS
1
7
SS
1
6
SS
1
5
SS
1
4
SS
1
3
SS
1
2
SS
1
1
SS
1
0
SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] SSx
SLEEP STATE OF GPx – If programmed as an output:
0 – Pin is driven to a zero during sleep mode
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.
Table 3-17. PGSR1 Bit Definitions
0x40F0_0024 PGSR1 Clocks and Power Manager
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS6
3
SS6
2
SS6
1
SS6
0
SS5
9
SS5
8
SS5
7
SS5
6
SS5
5
SS5
4
SS5
3
SS5
2
SS5
1
SS5
0
SS4
9
SS4
8
SS4
7
SS4
6
SS4
5
SS4
4
SS4
3
SS4
2
SS4
1
SS4
0
SS3
9
SS3
8
SS3
7
SS3
6
SS3
5
SS3
4
SS3
3
SS3
2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] SSx
SLEEP STATE OF GPx – If programmed as an output:
0 – Pin is driven to a zero during sleep mode
1 – Pin is driven to a one during sleep mode
Cleared by hardware, watchdog, and GPIO resets.
Table 3-18. PSPR Bit Definitions
0x40F0_0008 PSPR Clocks and Power Manager
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[31:0] SP
SCRATCH PAD:
32-bit word is preserved in sleep mode.
Cleared by hardware, watchdog, and GPIO resets.