Figure 6-29. alternate bus master mode, Figure 6-30. variable latency io, Figure 6-29 – Intel PXA26X User Manual
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Intel® PXA26x Processor Family Developer’s Manual
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Memory Controller
Figure 6-29. Alternate Bus Master Mode
Figure 6-30. Variable Latency IO
PXA26x Processor Family
EXTERNAL SYSTEM
MB
R
E
Q
MB
GN
T
GPIO<13> (MBGNT)
GPIO<14> (MBREQ)
nSDCS(0)
nWE
nSDRAS
nSDCAS
MD[31:0]
MA[25:0]
SDCLK<1>
DQM[3:0]
SDCKE<1>
Memory
Controller
External
SDRAM
Bank 0
Companion
Chip
GPIO
Block
PXA26x Processor Family
EXTERNAL SYSTEM
nCS(0,1,2,3,4,5)
nPWE
nOE
RDY
MD[31:0]
MA[25:0]
DQM[3:0]
Companion
Chip
Memory
Controller