Intel PXA26X - Manual (Page 36)

2-6 Intel® PXA26x Processor Family Developer’s Manual
System Architecture
Loads and stores to internal addresses are generally completed more quickly than those issued to
external addresses. The difference in completion time allows one operation to be received before
another operation, but completed after the second operation.
In the following sequence, the store to the address in r4 is completed before the store to the address
in r2 because the first store waits for memory in the queue while the second is not delayed.
str r1, [r2] ; store to external memory address [r2].
str r3, [r4] ; store to internal (on-chip) memory address [r4].
If the two stores are control operations that must be completed in order, the recommended sequence
is to insert a load to an unbuffered, uncached memory page followed by an operation that depends
on data from the load:
str r1, [r2] ; first store issued
ldr r5, [r6] ; load from external unbuffered, uncached address ([r2] if possible)
mov r5, r5 ; nop stalls until r5 is loaded
str r3, [r4] ; second store completes in program order
2.5 Semaphores
The Swap (SWP) and Swap Byte (SWPB) instructions, as described in the ARM* architecture
reference, may be used for semaphore manipulation. No on-chip master or process can access a
memory location between the load and store portion of a SWP or SWPB to the same location.
Note: Semaphore coherency may be interrupted because an external companion chip that uses the
MBREQ/MBGNT handshake can take ownership of the bus during a locked sequence. To allow
semaphore manipulation by external companion chips, the software must manage coherency.
2.6 Interrupts
The interrupt controller is described in detail in Section 4.2, “Interrupt Controller” . All on-chip
interrupts are enabled, masked, and routed to the core fast interrupt request (FIQ) or interrupt
request (IRQ). Each interrupt is enabled or disabled at the source through an interrupt mask bit.
Generally, all interrupt bits in a unit are ORed together and present a single value to the interrupt
controller.
Each interrupt goes through the Interrupt Controller Mask Register and then the Interrupt
Controller Level Register directs the interrupt into either the IRQ or FIQ. If an interrupt is taken,
the software may read the Interrupt Controller Pending Register to identify the source. After it
identifies the interrupt source, the software is responsible for servicing the interrupt and clearing it
in the source unit before exiting the service routine.