Intel PXA26X - Manual (Page 379)

Intel® PXA26x Processor Family Developer’s Manual 10-13
Universal Asynchronous Receiver/Transmitter
Table 10-11. FIFO Control Register – FCR
Base+0x08 FIFO Control Register UART
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
eser
ve
d
ITL
R
eser
ve
d
R
eser
ve
d
R
eser
ve
d
R
E
SETTF
RE
SETR
F
T
R
FIFO
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Write only
Bits Name Description
31:8 — Reserved
7:6 ITL
INTERRUPT TRIGGER LEVEL:
When the number of bytes in the receiver FIFO equals the interrupt trigger level
programmed into this field and the Received Data Available Interrupt is enabled via the
IER, an interrupt is generated and appropriate bits are set in the IIR. The receive DMA
request is also generated when the trigger level is reached.
0b00 – 1 byte or more in FIFO causes interrupt (Not valid in DMA mode)
0b01 – 8 bytes or more in FIFO causes interrupt and DMA request
0b10 – 16 bytes or more in FIFO causes interrupt and DMA request
0b11 – 32 bytes or more in FIFO causes interrupt and DMA request
5:3 — Reserved
2 RESETTF
RESET TRANSMITTER FIFO:
When RESETTF is set to 1, all the bytes in the transmitter FIFO are cleared. The TDRQ bit
in the LSR is set and the IIR shows a transmitter requests data interrupt, if the TIE bit in the
IER register is set. The transmitter shift register is not cleared and it completes the current
transmission.
0 – Writing 0 has no effect
1 – The transmitter FIFO is cleared
1 RESETRF
RESET RECEIVER FIFO:
When RESETRF is set to 1, all the bytes in the receiver FIFO are cleared. The DR bit in the
LSR is reset to 0. All the error bits in the FIFO and the FIFOE bit in the LSR are cleared.
Any error bits, OE, PE, FE or BI, that had been set in LSR are still set. The receiver shift
register is not cleared. If the IIR had been set to Received Data Available, it is cleared.
0 – Writing 0 has no effect
1 – The receiver FIFO is cleared
0 TRFIFOE
TRANSMIT AND RECEIVE FIFO ENABLE:
TRFIFOE enables/disables the transmitter and receiver FIFOs. When TRFIFOE = 1, both
FIFOs are enabled (FIFO Mode). When TRFIFOE = 0, the FIFOs are both disabled (non-
FIFO Mode). Writing a 0 to this bit clears all bytes in both FIFOs. When changing from
FIFO mode to non-FIFO mode and vice versa, data is automatically cleared from the
FIFOs. This bit must be 1 when other bits in this register are written or the other bits are not
programmed.
0 – FIFOs are disabled
1 – FIFOs are enabled