Intel PXA26X - Manual (Page 21)

Intel® PXA26x Processor Family Developer’s Manual xxi
Contents
12-27 UDC Endpoint x Data Register, Where x is 1, 6, or 11 ..........................................................12-47
12-28 UDC Endpoint x Data Register, Where x is 2, 7, or 12 ..........................................................12-48
12-29 UDC Endpoint x Data Register, where x is 3, 8, or 13...........................................................12-48
12-30 UDC Endpoint x Data Register, Where x is 4, 9, or 14 ..........................................................12-49
12-31 UDC Endpoint x Data Register, Where x is 5, 10, or 15........................................................12-49
12-32 UDC Control, Data, and Status Register Locations...............................................................12-50
13-1 External Interface to Codecs ...................................................................................................13-2
13-2 Supported Data Stream Formats.............................................................................................13-3
13-3 Slot 1 Bit Definitions.................................................................................................................13-7
13-4 Slot 2 Bit Definitions.................................................................................................................13-7
13-5 Input Slot 1 Bit Definitions......................................................................................................13-10
13-6 Input Slot 2 Bit Definitions......................................................................................................13-11
13-7 Register Mapping Summary ..................................................................................................13-19
13-8 Global Control Register .........................................................................................................13-20
13-9 Global Status Register...........................................................................................................13-22
13-10 PCM-Out Control Register.....................................................................................................13-24
13-11 PCM-In Control Register (PICR)............................................................................................13-24
13-12 PCM-Out Status Register ......................................................................................................13-25
13-13 PCM_In Status Register ........................................................................................................13-25
13-14 Codec Access Register .........................................................................................................13-26
13-15 PCM Data Register................................................................................................................13-26
13-16 Mic-In Control Register ..........................................................................................................13-27
13-17 Mic-In Status Register ...........................................................................................................13-28
13-18 Mic-In Data Register ..............................................................................................................13-28
13-19 Modem-Out Control Register.................................................................................................13-29
13-20 Modem-In Control Register....................................................................................................13-30
13-21 Modem-Out Status Register ..................................................................................................13-30
13-22 Modem-In Status Register .....................................................................................................13-31
13-23 Modem Data Register............................................................................................................13-31
13-24 Address Mapping for Codec Registers ..................................................................................13-33
14-1 External Interface to CODEC...................................................................................................14-2
14-2 Supported Sampling Frequencies ...........................................................................................14-6
14-3 SACR0 Bit Descriptions...........................................................................................................14-8
14-4 FIFO Write/Read table...........................................................................................................14-10
14-5 TFTH and RFTH Values for DMA Servicing ..........................................................................14-10
14-6 SACR1 Bit Descriptions.........................................................................................................14-11
14-7 SASR0 Bit Descriptions .........................................................................................................14-12
14-8 SADIV Bit Descriptions ..........................................................................................................14-13
14-9 SAICR Bit Descriptions..........................................................................................................14-14
14-10 SAIMR Bit Descriptions .........................................................................................................14-14
14-11 SADR Bit Descriptions...........................................................................................................14-15
14-12 Register Memory Map ...........................................................................................................14-16
15-1 Command Token Format.........................................................................................................15-2
15-2 MMC Data Token Format ........................................................................................................15-2
15-3 SPI Data Token Format ...........................................................................................................15-2
15-4 MMC Signal Description ..........................................................................................................15-5
15-5 MMC Controller Registers .....................................................................................................15-21
15-6 MMC_STRPCL Register........................................................................................................15-22
15-7 MMC_STAT Register.............................................................................................................15-22
15-8 MMC_CLK Register...............................................................................................................15-24