Intel PXA26X - Manual (Page 432)

12-22 Intel® PXA26x Processor Family Developer’s Manual
Universal Serial Bus Device Controller
address for the 16 x 8 data FIFO that can be used to transmit and receive data. Endpoint 0 also has
a write count register that is used to determine the number of bytes the USB host controller has sent
to endpoint 0.
12.6.1 UDC Control Register
The UDC control register (UDCCR) contains seven control bits: one to enable the UDC, one to
show activity, and five to show status and associated control functions.
12.6.1.1 UDC Enable
The UDC Enable (UDE) bit enables the UDC. When UDE is set to a 1, the UDC is enabled for
USB serial transmission or reception. When UDE is set to a 0, the UDC is disabled and the UDC+
and UDC- pins are three-stated. This means that the UDC ignores all activity on the USB bus.
If UDE is set to a 0 the entire UDC design is reset. If the reset occurs while the UDC is actively
transmitting or receiving data, it stops immediately and the remaining bits in the transmit or receive
serial shifter are reset. All entries in the transmit and receive FIFO are also reset.
12.6.1.2 UDC Active
The read-only UDC Active (UDA) bit can be read to determine if the UDC is currently active or in
a USB reset. This bit is only valid when the UDC is enabled. A zero indicates that the UDC is
currently receiving a USB reset from the host. A one indicates that the UDC is currently involved
in a transaction.
12.6.1.3 UDC Resume (RSM)
When the UDC is in a suspend state, this bit can be written to force the UDC into a non-idle state
(K state) for 3 ms to perform a remote-wake-up operation. If the host PC does not start a wake-up
sequence in 3 ms, the UDC returns to the suspend mode. This bit is a trigger bit for the UDC and is
automatically cleared.
12.6.1.4 Resume Interrupt Request (RESIR)
The resume interrupt request bit is set if the SRM bit in the UDC control register is cleared, the
UDC is currently in the suspended state, and the USB is driven with resume signalling.
12.6.1.5 Suspend Interrupt Request (SUSIR)
The suspend interrupt request register is set when the USB remains idle for more than 6 ms. The
SUSIR bit retains state so software can determine that the USB is idle. If SRM is zero, SUSIR
being set will not generate an interrupt but status continues to be updated.
12.6.1.6 Suspend/Resume Interrupt Mask (SRM)
The suspend/resume interrupt mask (SRM) masks or enables the suspend interrupt request to the
interrupt controller. When SRM is 1, the interrupt is masked and the setting of SUSIR will not
generate an interrupt. When SRM is 0, the setting of SUSIR generates an interrupt when the USB is
idle for more than 6ms. Programming SRM does not affect the state of SUSIR.