Intel PXA26X - Manual (Page 451)

Intel® PXA26x Processor Family Developer’s Manual 12-41
Universal Serial Bus Device Controller
12.6.10.7 Endpoint 6 Interrupt Request (IR6)
The interrupt request bit gets set if the IM6 bit in the UDC interrupt control register is cleared and
the IN packet complete (TPC) in UDC endpoint 6 control/status register gets set. The IR6 bit is
cleared by writing a one to it.
12.6.10.8 Endpoint 7 Interrupt Request (IR7)
The interrupt request bit is set if the IM7 bit in the UDC interrupt control register is cleared and the
OUT packet ready bit (RPC) in the UDC endpoint 7 control/status register is set. The IR7 bit is
cleared by writing a 1 to it.
12.6.11 UDC Status/Interrupt Register 1 (USIR1)
12.6.11.1 Endpoint 8 Interrupt Request (IR8)
The interrupt request bit is set if the IM8 bit in the UDC interrupt control register is cleared and the
IN packet complete (TPC) or Transmit Underrun (TUR) in UDC endpoint 8 control/status register
is set. The IR8 bit is cleared by writing a 1 to it.
Table 12-21. UDC Status / Interrupt Register 0
0h 4060 0058 USIR0 Read/Write and Read-Only
Bit 31:8 7 6 5 4 3 2 1 0
Reserved IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0
Rese
t
X 0 0 0 0 0 0 0 0
Bits Name Description
0 IR0
INTERRUPT REQUEST ENDPOINT 0 (read/write 1 to clear):
1 – Endpoint 0 needs service.
1 IR1
INTERRUPT REQUEST ENDPOINT 1 (read/write 1 to clear):
1 – Endpoint 1 needs service.
2 IR2
INTERRUPT REQUEST ENDPOINT 2 (read/write 1 to clear):
1 – Endpoint 2 needs service.
3 IR3
INTERRUPT REQUEST ENDPOINT 3 (read/write 1 to clear):
1 – Endpoint 3 needs service.
4 IR4
INTERRUPT REQUEST ENDPOINT 4 (read/write 1 to clear):
1 – Endpoint 4 needs service.
5 IR5
INTERRUPT REQUEST ENDPOINT 5 (read/write 1 to clear):
1 – Endpoint 5 needs service.
6 IR6
INTERRUPT REQUEST ENDPOINT 6 (read/write 1 to clear):
1 – Endpoint 6 needs service.
7 IR7
INTERRUPT REQUEST ENDPOINT 7 (read/write 1 to clear):
1 – Endpoint 7 needs service.
31:8 — Reserved for future use