Table 17-9, “interrupt identification register – Intel PXA26X User Manual
Page 600
17-16
Intel® PXA26x Processor Family Developer’s Manual
Hardware UART
shows the priority, type, and source of the Interrupt Identification Register Interrupts. It
also gives the reset condition used to deassert the Interrupts. Bits (0-3) of the IIR represent priority
encoded interrupts. Bits (4-7) do not.
3
R
TOD
TIME OUT DETECTED (See
Section 17.4.2.1.2, “Character Timeout
):
0 – No time out Interrupt is pending
1 – Time out Interrupt is pending. (FIFO mode only)
2:1
R
IID[1:0]
INTERRUPT SOURCE ENCODED:
00
–
Modem Status (CTS, DSR, RI, DCD modem signals changed state)
01
–
Transmit FIFO requests data
10
–
Received Data Available
11
–
Receive error (overrun, parity, framing, break, FIFO error. See
0
R
nIP
INTERRUPT PENDING:
0 – Interrupt is pending. (Active low)
1 – No Interrupt is pending
Table 17-8.
IIR Bit Definitions (Sheet 2 of 2)
Physical Address
0x4160_0008
Interrupt Identification Reg. (IIR)
PXA26x Processor Family Hardware
UART
User
Settings
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
FIFO
ES
R
eser
ved
AB
L
TO
D
IID
nI
P
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
?
0
0
0
0
1
Bits
Access
Name
Description
Table 17-9. Interrupt Identification Register Decode (Sheet 1 of 2)
Interrupt ID bits
Interrupt SET/RESET Function
3
2
1
0
Priority
Type
Source
RESET Control
nIP
0
0
0
1 -
None
No Interrupt is pending.
—
IID[11] 0
1
1
0 Highest
Receiver Line
Status
Overrun Error, Parity Error, Framing
Error, Break Interrupt.
Reading the Line Status Register.
IID[10] 0
1
0
0
Second
Highest
Received Data
Available.
Non-FIFO mode – Receive Buffer is
full.
Non-FIFO mode – Reading the
Receiver Buffer Register.
FIFO mode – trigger threshold was
reached.
FIFO mode – Reading bytes until
receiver FIFO drops below trigger
threshold or setting RESETRF bit in the
FCR.
TOD
1
1
0
0
Second
Highest
Character
Timeout
indication.
FIFO mode only – At least 1 character
is left in the receive buffer indicating
trailing bytes.
Reading the receiver FIFO or setting
RESETRF bit in the FCR.