Intel PXA26X - Manual (Page 22)

xxii Intel® PXA26x Processor Family Developer’s Manual
Contents
15-9 MMC_SPI Register ................................................................................................................15-24
15-10 MMC_CMDAT Register .........................................................................................................15-25
15-11 MMC_RESTO Register .........................................................................................................15-27
15-12 MMC_RDTO Register ...........................................................................................................15-27
15-13 MMC_BLKLEN Register ........................................................................................................15-28
15-14 MMC_NOB Register ..............................................................................................................15-28
15-15 MMC_PRTBUF Register .......................................................................................................15-29
15-16 MMC_I_MASK Register ........................................................................................................15-29
15-17 MMC_I_REG Register ...........................................................................................................15-31
15-18 MMC_CMD Register .............................................................................................................15-32
15-19 Command Index Values ........................................................................................................15-32
15-20 MMC_ARGH Register ...........................................................................................................15-34
15-21 MMC_ARGL Register ............................................................................................................ 15-34
15-22 MMC_RES, FIFO Entry .........................................................................................................15-35
15-23 MMC_RXFIFO, FIFO Entry ...................................................................................................15-35
15-24 MMC_TXFIFO, FIFO Entry....................................................................................................15-36
16-1 SSP Serial Port I/O Signals .....................................................................................................16-2
16-2 Programmable Serial Protocol (PSP) Parameters ................................................................16-12
16-3 SSCR0 Bit Definitions............................................................................................................ 16-19
16-4 SSCR1 Bit Definitions............................................................................................................ 16-21
16-5 SSPSP Bit Definitions............................................................................................................ 16-27
16-6 SSTO Bit Definitions..............................................................................................................16-29
16-7 SSITR Bit Definitions .............................................................................................................16-29
16-8 SSSR Bit Definitions..............................................................................................................16-31
16-9 SSDR Bit Definitions..............................................................................................................16-34
16-10 NSSP Register Address Map ................................................................................................16-35
16-11 ASSP Register Address Map ................................................................................................16-35
17-1 UART Signal Descriptions .......................................................................................................17-3
17-2 RBR Bit Definitions ................................................................................................................17-11
17-3 THR Bit Definitions ................................................................................................................17-11
17-4 Divisor Latch Register Low (DLL) Bit Definitions...................................................................17-12
17-5 Divisor Latch Register High (DLH) Bit Definitions .................................................................17-12
17-6 IER Bit Definitions..................................................................................................................17-13
17-7 Interrupt Conditions ...............................................................................................................17-15
17-8 IIR Bit Definitions ...................................................................................................................17-15
17-9 Interrupt Identification Register Decode ................................................................................17-16
17-10 FCR Bit Definitions ................................................................................................................17-17
17-11 FOR Bit Definitions ................................................................................................................17-19
17-12 ABR Bit Definitions ................................................................................................................17-20
17-13 ACR Bit Definitions ................................................................................................................17-21
17-14 LCR Bit Definitions ................................................................................................................17-22
17-15 LSR Bit Definitions.................................................................................................................17-24
17-16 MCR Bit Definitions ...............................................................................................................17-27
17-17 MSR Bit Definitions................................................................................................................17-29
17-18 SPR Bit Definitions ................................................................................................................17-29
17-19 ISR Bit Definitions..................................................................................................................17-30
17-20 HWUART Register Locations ................................................................................................17-31
18-1 SXCNFG Configuration for Internal Flash ...............................................................................18-3
18-2 RCR Values for Each PXA26x processor family Applications Processor Version ..................18-3