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8 transmit short packet (tsp) – Intel PXA26X User Manual

Page 438

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12-28

Intel® PXA26x Processor Family Developer’s Manual

Universal Serial Bus Device Controller

12.6.3.8

Transmit Short Packet (TSP)

The software uses the transmit short packet bit to indicate that the last byte of a data transfer to the
FIFO has occurred. This indicates to the UDC that a short packet or zero-sized packet is ready to
transmit. Software must not set this bit if a 64-byte packet is to be transmitted. When the data
packet is successful transmitted, the UDC clears this bit.

12.6.4

UDC Endpoint x Control/Status Register (UDCCSx), Where
x is 2, 7, or 12

The UDC endpoint x control/status register contains 7 bits that operate endpoint x, a Bulk OUT
endpoint.

Table 12-14. UDC Endpoint x Control Status Register, Where x is 1, 6 or 11

0h 4060 0014

UDCCS1

Read/Write

0h 4060 0028

UDCCS6

Read/Write

0h 4060 003C

UDCCS11

Read/Write

Bit

31:8

7

6

5

4

3

2

1

0

Reserved

TSP

Reserve

d

FST

SST

TUR

FTF

TPC

TFS

Rese

t

X

0

0

0

0

0

0

0

1

Bits

Name

Description

0

TFS

TRANSMIT FIFO SERVICE (read-only):

0 – Transmit FIFO has no room for new data

1 – Transmit FIFO has room for at least 1 complete data packet

1

TPC

TRANSMIT PACKET COMPLETE (read/write 1 to clear):

0 – Error/status bits invalid.

1 – Transmit packet has been sent and error/status bits are valid.

2

FTF

FLUSH Tx FIFO (always read 0/ write a 1 to set):

1 – Flush Contents of TX FIFO

3

TUR

TRANSMIT FIFO UNDERRUN (read/write 1 to clear):

1 – Transmit FIFO experienced an underrun.

4

SST

SENT STALL (read/write 1 to clear):

1 – STALL handshake was sent.

5

FST

FORCE STALL (read/write):

1 – Issue STALL handshakes to IN tokens.

6

Reserved

Always reads 0

7

TSP

TRANSMIT SHORT PACKET (always read 0/write 1to set):

1 – Short packet ready for transmission.

31:8

Reserved for future use