Intel PXA26X - Manual (Page 5)

Intel® PXA26x Processor Family Developer’s Manual v
Contents
4.1.2 GPIO Alternate Functions.....................................................................................4-3
4.1.3 GPIO Register Definitions.....................................................................................4-7
4.1.4 GPIO Register Locations ....................................................................................4-21
4.2 Interrupt Controller ...........................................................................................................4-22
4.2.1
Interrupt Controller Operation .............................................................................4-23
4.2.2 Interrupt Controller Register Definitions..............................................................4-24
4.2.3 Interrupt Controller Register Locations ...............................................................4-31
4.3 Real-Time Clock (RTC) ...................................................................................................4-32
4.3.1
Real-Time Clock Operation.................................................................................4-32
4.3.2 Real-Time Clock Register Definitions .................................................................4-32
4.3.3 Trim Procedure ...................................................................................................4-35
4.3.4 Real-Time Clock Register Locations...................................................................4-38
4.4 Operating System Timer ..................................................................................................4-38
4.4.1
Watchdog Timer Operation.................................................................................4-38
4.4.2 Operating System Timer Register Definitions.....................................................4-39
4.4.3 Operating System Timer Register Locations ......................................................4-42
4.5 Pulse Width Modulator.....................................................................................................4-43
4.5.1
Pulse Width Modulator Operation .......................................................................4-43
4.5.2 Register Descriptions..........................................................................................4-44
4.5.3 Pulse Width Modulator Output Wave Example...................................................4-47
4.5.4 Register Summary ..............................................................................................4-48
5 Direct Memory Access Controller .................................................................................................5-1
5.1 Direct Memory Access Description ....................................................................................5-1
5.1.1
Direct Memory Access Controller Channels .........................................................5-2
5.1.2 Signal Descriptions ...............................................................................................5-3
5.1.3 Direct Memory Access Channel Priority Scheme .................................................5-4
5.1.4 Direct Memory Access Descriptors.......................................................................5-6
5.1.5 Channel States .....................................................................................................5-9
5.1.6 Read and Write Order...........................................................................................5-9
5.1.7 Byte Transfer Order ............................................................................................5-10
5.1.8 Trailing Bytes ......................................................................................................5-11
5.2 Transferring Data .............................................................................................................5-11
5.2.1
Servicing Internal Peripherals .............................................................................5-12
5.2.2 Quick Reference for Direct Memory Access Programming ................................5-13
5.2.3 Servicing Companion Chips and External Peripherals .......................................5-14
5.2.4 Memory-to-Memory Moves .................................................................................5-16
5.3 Direct Memory Access Controller Registers ....................................................................5-17
5.3.1
DMA Interrupt Register .......................................................................................5-17
5.3.2 DMA Channel Control/Status Register ...............................................................5-17
5.3.3 DMA Request to Channel Map Registers ...........................................................5-19
5.3.4 DMA Descriptor Address Registers ....................................................................5-20
5.3.5 DMA Source Address Registers .........................................................................5-21
5.3.6 DMA Target Address Registers ..........................................................................5-22
5.3.7 DMA Command Registers ..................................................................................5-23
5.4 Examples .........................................................................................................................5-25
5.5 Direct Memory Access Controller Registers Locations....................................................5-28
6 Memory Controller ........................................................................................................................6-1
6.1 Overview ............................................................................................................................6-1