13 udc frame number low register (ufnlr), Table 12-24. udc frame number low register, 1 endpoint x byte count (bc[7:0]) – Intel PXA26X User Manual
Page 455

Intel® PXA26x Processor Family Developer’s Manual
12-45
Universal Serial Bus Device Controller
12.6.13
UDC Frame Number Low Register (UFNLR)
The UDC frame number low register is the eight least significant bits of the 11-bit frame number
contained in the last received SOF packet. The three remaining bits are located in the UFNHR.
This information is used for isochronous transfers. These bits are updated every SOF.
12.6.14
UDC Byte Count Register x (UBCRx), Where x is 2, 4, 7, 9,
12, or 14.
The byte count register maintains the remaining byte count in the active buffer of OUT
endpoint(x).
12.6.14.1
Endpoint x Byte Count (BC[7:0])
The byte count is updated after each byte is read. When software receives an interrupt that indicates
the endpoint has data, it can read the byte count register to determine the number of bytes that
remain to be read. The number of bytes that remain in the input buffer is equal to the byte count +1.
6
SIM
SOF INTERRUPT MASK:
0 – SOF interrupt enabled.
1 – SOF interrupt disabled.
7
SIR
SOF INTERRUPT REQUEST (read/write 1 to clear):
1 – SOF has been received.
31:8
—
Reserved for future use
Table 12-23. UDC Frame Number High Register (Sheet 2 of 2)
0h 4060 0060
UFNHR
Read
Bit
31:8
7
6
5
4
3
2
1
0
Reserved
SIR
SIM
IPE14
IPE9
IPE4
3-Bit Frame Number MSB
Rese
t
X
0
1
0
0
0
0
0
0
Bits
Name
Description
Table 12-24. UDC Frame Number Low Register
0h 4060 0064
UFNLR
Read-Only
Bit
31:8
7
6
5
4
3
2
1
0
Reserved
8-Bit Frame Number LSB
Reset
X
0
0
0
0
0
0
0
0
Bits
Name
Description
7:0
FNLSB
FRAME NUMBER LSB:
Least significant 8-bits of frame number associated with last received SOF.
31:8
—
Reserved for future use