Intel PXA26X - Manual (Page 444)

12-34 Intel® PXA26x Processor Family Developer’s Manual
Universal Serial Bus Device Controller
12.6.6.2 Receive Packet Complete (RPC)
The receive packet complete bit gets set by the UDC when an OUT packet is received. When this
bit is set, the IRx bit in the appropriate UDC status/interrupt register is set if receive interrupts are
enabled. This bit can be used to validate the other status/error bits in the endpoint(x) control/status
register. The UDCCSx[RPC] bit is cleared by writing a 1 to it.
12.6.6.3 Receive Overflow (ROF)
The receive overflow bit generates an interrupt on IRx in the appropriate UDC status/interrupt
register to alert the software that Isochronous data packets are being dropped because neither FIFO
buffer has room for them. This bit is cleared by writing a 1 to it.
12.6.6.4 DMA Enable (DME)
The DMA enable is used by the UDC to control the timing of the data received interrupt. If the bit
is set, the interrupt is asserted when the end of packet is received and the receive FIFO has less than
32 bytes of data in it. If the bit is not set, the interrupt is asserted when the end of packet is received
and all of the received data is still in the receive FIFO.
12.6.6.5 Bit 4 Reserved
Bit 4 is reserved for future use.
12.6.6.6 Bit 5 Reserved
Bit 5 is reserved for future use.
12.6.6.7 Receive FIFO Not Empty (RNE)
The receive FIFO not empty bit indicates that the receive FIFO has unread data in it. When the
UDCCSx[RPC] bit is set, this bit must be read to determine if there is any data in the FIFO that
DMA did not read. The receive FIFO must continue to be read until this bit clears or data will be
lost.
12.6.6.8 Receive Short Packet (RSP)
The receive short packet bit is used by the UDC to indicate that the received OUT packet in the
active buffer currently being read is a short packet or zero-sized packet. This bit is updated by the
UDC after the last byte is read from the active buffer and reflects the status of the new active
buffer. If UDCCSx[RSP] is a one and UDCCSx[RNE] is a zero, it indicates a zero-length packet. If
a zero-length packet is present, the core must not read the data register. UDCCSx[RSP] clears
when the next OUT packet is received.