Intel PXA26X - Manual (Page 246)

6-56 Intel® PXA26x Processor Family Developer’s Manual
Memory Controller
6.8.6 FLASH Memory Interface
The processor provides an SRAM-like interface for access of flash memory. The RDF fields in the
MSCx registers are the latency for each read access to non-burst flash, or the first read access to
burst flash. The RDF fields also control the nWE low time during a write cycle to flash. The RDN
field controls subsequent read access times to burst flash and the nWE low time during a write
cycle to non-burst flash. RRR is the time from nCS deassertion after a read to the start of a read
from a different memory, or after a write to another memory access.
Reads from flash memory have these requirements:
• Because flash defaults to read-array mode, burst reads are permitted out of flash, which allows
instruction caching and DMA reads from flash.
• Software partitions commands and data and writes the commands to flash before the read. The
memory controller does not insert any commands before flash reads.
Writes to flash memory have these requirements:
• Flash memory space must be uncache-able and unbuffered.
• Burst writes to flash are not supported. Writes to flash must be exactly the width of the
populated flash devices on the data bus and must be a burst length of one write, for example no
byte writes to a 32-bit bus. The allowable writes are: 2 bytes written to a 16-bit bus, and
4 bytes written to a 32-bit bus.
• For asynchronous writes to flash, the command and data must be given in separate write
instructions to the memory controller, the first carries the command, the next carries the data.
• The memory controller does not insert any commands before flash writes. Software must write
the commands and data in the correct order.
• No flash writes can be bursts. DMA must never write to flash.
For writes to flash, if all byte enables are turned off (masking out the data, DQM = 1111), the write
enable is suppressed (nWE = 1) for the write beat, which can result in a period when nCS is
asserted, but neither nOE nor nWE is asserted. This happens when there is a 1-beat write to flash,
but all byte enables are turned off.
6.8.6.1 Flash Memory Timing Diagrams and Parameters
Non-burst flash reads have the same timing as non-burst ROMs reads. Figure 6-20 shows the
timing for writes to non-burst asynchronous flash.