Intel PXA26X - Manual (Page 60)

2-30 Intel® PXA26x Processor Family Developer’s Manual
System Architecture
0x40E0 0038 GRER2 GPIO Rising-Edge Detect Register GPIO<80:64>
0x40E0 003C GFER0 GPIO Falling-Edge Detect Register GPIO<31:0>
0x40E0 0040 GFER1 GPIO Falling-Edge Detect Register GPIO<63:32>
0x40E0 0044 GFER2 GPIO Falling-Edge Detect Register GPIO<80:64>
0x40E0 0048 GEDR0 GPIO Edge Detect Status Register GPIO<31:0>
0x40E0 004C GEDR1 GPIO Edge Detect Status Register GPIO<63:32>
0x40E0 0050 GEDR2 GPIO Edge Detect Status Register GPIO<80:64>
0x40E0 0054 GAFR0_L GPIO Alternate Function Select Register GPIO<15:0>
0x40E0 0058 GAFR0_U GPIO Alternate Function Select Register GPIO<31:16>
0x40E0 005C GAFR1_L GPIO Alternate Function Select Register GPIO<47:32>
0x40E0 0060 GAFR1_U GPIO Alternate Function Select Register GPIO<63:48>
0x40E0 0064 GAFR2_L GPIO Alternate Function Select Register GPIO<79:64>
0x40E0 0068 GAFR2_U GPIO Alternate Function Select Register GPIO 80
Power
Manager and
Reset
Control
0x40F0 0000
0x40F0 0000 PMCR Power Manager Control Register
0x40F0 0004 PSSR Power Manager Sleep Status Register
0x40F0 0008 PSPR Power Manager Scratch Pad Register
0x40F0 000C PWER Power Manager Wake-up Enable Register
0x40F0 0010 PRER Power Manager GPIO Rising-Edge Detect Enable Register
0x40F0 0014 PFER Power Manager GPIO Falling-Edge Detect Enable Register
0x40F0 0018 PEDR Power Manager GPIO Edge Detect Status Register
0x40F0 001C PCFR Power Manager General Configuration Register
0x40F0 0020 PGSR0 Power Manager GPIO Sleep State Register for GP[31-0]
0x40F0 0024 PGSR1 Power Manager GPIO Sleep State Register for GP[63-32]
0x40F0 0028 PGSR2 Power Manager GPIO Sleep State Register for GP[84-64]
0x40F0 002C — reserved
0x40F0 002C — reserved
0x40F0 0030 RCSR Reset Controller Status Register
0x40F0 0034 PMFWR Power Manager Fast Sleep Walk-up Configuration Register
SSP 0x4100 0000
0x4100 0000 SSCR0 SSP Control Register 0
0x4100 0004 SSCR1 SSP Control Register 1
0x4100 0008 SSSR SSP Status Register
0x4100 000C SSITR SSP Interrupt Test Register
0x4100 0010 SSDR (Write / Read) SSP Data Write Register/SSP Data Read Register
MMC
Controller
0x4110 0000
0x4110 0000 MMC_STRPCL Control to start and stop MMC clock
Table 2-8. Register Address Summary (Sheet 10 of 13)
Unit Address Register Symbol Register Description