Table 4-34. icip register bitmap, Table 4-35. icfp register bitmap, 5 interrupt controller pending register (icpr) – Intel PXA26X User Manual
Page 135: Table 4-34, Table 4-35
Intel® PXA26x Processor Family Developer’s Manual
4-27
System Integration Unit
4.2.2.5
Interrupt Controller Pending Register (ICPR)
The ICPR is a 32-bit read-only register that shows all active interrupts in the system. These bits are
not affected by the state of the mask register (ICMR). Clearing the interrupt status bit at the source,
automatically clears the corresponding ICPR flag, provided there are no other interrupt status bits
set within the source unit.
shows the bitmap of the Interrupt Controller Pending
Register.
shows the pending interrupt source assigned to each bit position in the ICPR. Also
included in the table are the source units for the interrupts and the number of second-level
interrupts associated with each. For more information on the second-level interrupts, see the
section that corresponds to its name in the Source Unit column.
Table 4-34. ICIP Register Bitmap
Physical Address
0x40D0_0000
Interrupt Controller IRQ Pending
Register (ICIP)
System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
IP31
IP30
IP29
IP28
IP27
IP26
IP25
IP24
IP23
IP22
IP21
IP20
IP19
IP18
IP17
IP16
IP15
IP14
IP13
IP12
IP1
1
IP10
IP9
IP8
IP7
R
eser
ved
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
Bits
Name
Description
<31:7>
IP[x]
IRQ PENDING ‘X’ (where x = 7 through 31):
0 – IRQ NOT requested by any enabled source.
1 – IRQ requested by an enabled source.
<6:0>
—
Reserved
Table 4-35. ICFP Register Bitmap
Physical Address
0x40D0_000C
Interrupt Controller FIQ Pending
Register (ICFP)
System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
FP
31
FP
30
FP
29
FP
28
FP
27
FP
26
FP
25
FP
24
FP
23
FP
22
FP
21
FP
20
FP
19
FP
18
FP
17
FP
16
FP
15
FP
14
FP
13
FP
12
FP
1
1
FP
10
FP
9
FP
8
FP
7
Reserved
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
Bits
Name
Description
<31:7>
FP[x]
FIQ PENDING ‘X’ (where x = 7 through 31):
0 – FIQ NOT requested by any enabled source.
1 – FIQ requested by an enabled source.
<6:0>
—
Reserved