Intel PXA26X - Manual (Page 161)

Intel® PXA26x Processor Family Developer’s Manual 5-3
Direct Memory Access Controller
Channel information must be maintained on a per-channel basis and is contained in the DMAC
registers shown in
Table 5-13, “DMA Controller Registers” on page 5-28 . The DMAC supports
two methods of loading the DMAC registers, No-Descriptor and Descriptor Fetch Modes. The
fetch modes are discussed in further detail in
Section 5.1.4, “Direct Memory Access Descriptors”
on page 5-6 .
Software must ensure cache coherency when it configures the DMA channels. The DMAC does
not check the cache so target and source addresses must be configured as non-cacheable in the
Memory Management Unit.
Each demand for data that a peripheral generates results in a read or write to memory. A peripheral
must not request a DMA transfer unless it is prepared to read or write the full data block (8, 16, or
32 bytes) and it is equipped to handle reads and writes less than a full data block. Reads and writes
less than a full data block can occur at the end of a DMA transfer.
5.1.2 Signal Descriptions
The DREQ[1:0], PREQ[37:0] and DMA_IRQ signals are controlled by the DMAC as indicated in
Table 5-1 .
5.1.2.1 DREQ[1:0] and PREQ[37:0] Signals
The external companion chip asserts the positive edge triggered DREQ[1:0] signals when a DMA
transfer request is needed. The DREQ[1:0] signal must remain asserted for four MEMCLKs to
allow the DMA to recognize the 0 to 1 transition. When the DREQ[1:0] signals are deasserted, they
must remain deasserted for at least four MEMCLKs. The DMAC registers the transition from 0 to
1 to identify a new request. The external companion chip must not assert another DREQ until the
previous DMA data transfer starts.
Figure 5-2. DREQ timing requirements
Table 5-1. DMAC Signal List
Signal
Signal Type
In/Out
To/From Definition
DREQ[1:0] Input Pins
External companion chip request lines. DMA detects the
positive edge of this signal as a request.
DMA_IRQ Output
Interrupt
Controller
Active high signal indicating an interrupt.
PREQ[37:0] Input
On-chip
peripherals
Internal peripheral DMA request lines. On chip peripherals
send requests using the PREQ signals.
The DMAC does not sample the PREQ signals until it
completely finishes the data transfer from peripheral to the
memory.
dreq_deassert_min dreq_deassert_min dreq_assert_min dreq_assert_min
mem_clk
DREQ