Intel PXA26X - Manual (Page 401)

Intel® PXA26x Processor Family Developer’s Manual 11-7
Fast Infrared Communication Port
At the end of each transmitted frame, the FICP sends a pulse called the serial infrared interaction
pulse (SIP). A SIP must be sent at least every 500 ms to ensure that low-speed devices (115.2 Kbps
and slower) do not interfere with devices that transmit at higher speeds. The SIP simulates a start
bit that causes low-speed devices to stay off the air for at least another 500 ms. The SIP pulse
forces the transmit data pin high for 1.625 µs and low for 7.375 µs (the total SIP period is 9.0 µs).
After the SIP period, the preamble is transmitted continuously to indicate to the off-chip receiver
that the FICP’s transmitter is in the idle state. The preamble is transmitted until new data is
available in the transmit FIFO or the FICP’s transmitter is disabled. At least one frame must be
completed every 500 ms to ensure that an SIP pulse can keep low-speed devices from interrupting
the transmission. Because most IrDA compatible devices produce an SIP after each frame
transmitted, software only needs to ensure that a frame is either transmitted or received by the FICP
every 500 ms. Frame length does not represent a significant portion of the 500 ms timeframe in
which an SIP must be produced. At 4.0 Mbps, the longest frame allowed is 16,568 bits, which
takes just over 4 ms to transmit. The FICP also issues an SIP when the transmitter is first enabled.
This ensures that low-speed devices do not interfere as the FICP transmits its data.
If software disables the FICP’s transmitter during operation, data transmission stops immediately,
the serial shifter and transmit FIFO are cleared, and the SIU takes control of the transmit data pin.
The transmit data output’s polarity must be properly reprogrammed if the pin is used as a GPIO
output.
11.2.10 Transmit and Receive FIFOs
The transmit FIFO is 128 entries deep and 8 bits wide. The receive FIFO is 128 entries deep,
11 bits wide. The receive FIFO uses 3 bits of its entries as status bits. The transmit FIFO and the
receive FIFO use two separate, dedicated DMA requests.
When the transmit FIFO has 32 or more empty bytes, the transmit DMA request and an interrupt (if
enabled) are generated and tell the processor to send more data to the FIFO. When the transmit
FIFO is full, any more data from the processor is lost. When the receive FIFO reaches its trigger
level (programmed in ICCR2), the receive DMA request (if no errors are found within the entries)
and an interrupt (if enabled) are generated and tell the processor to remove the data from the FIFO.
If an error is found in the FIFO’s trigger level range, DMA requests are disabled and an interrupt is
generated to ensure that the DMAC does not read the error bytes.
The number of bytes being transferred for each DMA request is programmed in the DMAC and
can be 8, 16, or 32 bytes. The receive FIFO’s trigger level must be set so the FIFO has enough data
for the DMAC to read. The transmit FIFO does not have programmable trigger levels. Its DMA
request is generated when the FIFO has 32 or more empty bytes, regardless of the DMA transfer
size.
The DMA controller must not service the receive FIFO when the processor tries to respond to an
receive error interrupt. The error interrupt may be set high before the DMA controller finishes the
previous request. The processor can not remove the error bytes until the DMAC has completed its
transaction.
11.2.11 Trailing or Error Bytes in the Receive FIFO
When the number of bytes in the receive FIFO is less than the trigger level and no more data is
being received, the bytes in the FIFO are called trailing bytes. Trailing bytes do not trigger a
receive DMA request. Instead they trigger the end/error in FIFO, ICSR0[EIF] interrupt, which is
nonmaskable. When ICSR0[EIF] is set, DMA requests are disabled. The core must read bytes from
the FIFO until ICSR0[EIF] is cleared.