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Table 7-8. lcd dma frame source address registers, 4 lcd dma frame id registers (fidrx), Table 7-9. lcd frame id registers – Intel PXA26X User Manual

Page 307

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Intel® PXA26x Processor Family Developer’s Manual

7-39

Liquid Crystal Display Controller

memory location at the beginning of the palette data. The size of the palette data must be four 16-
bit entries for 1- and 2-bit pixels, sixteen 16-bit entries for 4-bit pixels, or 256 16-bit entries for 8-
bit pixels. If this is a pixel-data descriptor, FSADRx points to the beginning of the frame buffer in
memory. This address is incremented as the DMAC fetches from memory. If desired, the DMA
Frame ID Register can hold the initial frame source address.

Table 7-8

shows the bit layout.

These read-only registers are loaded indirectly via the frame descriptors, as described in

Section 7.6.5.1, “Frame Descriptors”

.

7.6.5.4

LCD DMA Frame ID Registers (FIDRx)

Registers FIDR0 and FIDR1, corresponding to DMA channels 0 and 1, contain an ID field that
describes the current frame. The particular use of this field is up to you. This ID register is copied
to the LCD Controller Interrupt ID Register when an interrupt occurs.

Table 7-9

shows the bit

layout.

These read-only registers are loaded indirectly via the frame descriptors, as described in

Section 7.6.5.1, “Frame Descriptors”

.

Table 7-8. LCD DMA Frame Source Address Registers

Physical Address

channel 0: 0x4400_0204
channel 1: 0x4400_0214

LCD DMA Frame Source Address

Registers

LCD Controller

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Frame Source Address

Reset

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Bits

Name

Description

31:0

Frame

Source

Address

ADDRESS OF THE PALETTE OR PIXEL FRAME DATA IN MEMORY:

Bits [2:0] must be zero for proper memory alignment.

Table 7-9. LCD Frame ID Registers

Physical Address

channel 0: 0x4400_0208
channel 1: 0x4400_0218

LCD DMA Frame ID Registers

LCD Controller

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Frame ID

Reserved

Reset

?

?

?

?

?

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X

X

X

Bits

Name

Description

31:3

Frame ID

FRAME ID

2:0

Reserved