4 interrupt enable register (ier), Table 17-6. ier bit definitions (sheet 1 of 2) – Intel PXA26X User Manual
Page 597
Intel® PXA26x Processor Family Developer’s Manual
17-13
Hardware UART
17.5.4
Interrupt Enable Register (IER)
The IER enables the five types of interrupts that set a value in the Interrupt Identification Register
(IIR). To disable an interrupt, software must clear the appropriate bit in the IER. Software can
enable some interrupts by setting the appropriate bit.
The Character Timeout Indication interrupt is separated from the received data available interrupt
to ensure that the processor and the DMA controller do not service the receive FIFO at the same
time. When a Character Timeout Indication interrupt occurs, the processor must handle the data in
the receive FIFO through programmed I/O.
Enabling DMA requests also enables a separate error interrupt. For additional information see
.
Bit 7 of the IER is used to enable DMA requests. The IER also contains the unit enable and NRZ
coding enable control bits. Bits 7 through 4 are used differently from the standard 16550A register
definition. The IER bit definitions are shown in
.
Note:
MCR[OUT2] is a global interrupt enable, and must be set to enable UART interrupts.
Table 17-6.
IER Bit Definitions (Sheet 1 of 2)
Physical Address
0x4160_0004
Interrupt Enable Reg. (IER)
PXA26x Processor Family Hardware
UART
User
Settings
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
DM
AE
UU
E
NR
Z
E
RT
OI
E
MI
E
RL
S
E
TIE
RA
VI
E
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
Bits
Access
Name
Description
31:8
N/A
—
Reserved – Read as unknown and must be written as zero.
7
R/W
DMAE
DMA REQUESTS ENABLE:
0 – DMA requests are disabled
1 – DMA requests are enabled
6
R/W
UUE
UART UNIT ENABLE:
0 – the unit is disabled
1 – the unit is enabled
5
R/W
NRZE
NRZ CODING ENABLE:
NRZ encoding/decoding is only used in UART mode, not in infrared mode.
If the slow infrared receiver or transmitter is enabled, NRZ coding is
disabled.
0 – NRZ coding disabled
1 – NRZ coding enabled
4
R/W
RTOIE
RECEIVER TIME OUT INTERRUPT ENABLE (Source IIR[TOD]):
0 – Receiver data Time out Interrupt disabled
1 – Receiver data Time out Interrupt enabled