Intel PXA26X - Manual (Page 442)

12-32 Intel® PXA26x Processor Family Developer’s Manual
Universal Serial Bus Device Controller
12.6.5.3 Flush Tx FIFO (FTF)
The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx FIFO bit is
set when software writes a 1 to it or when the host performs a SET_CONFIGURATION or
SET_INTERFACE. The bit’s read value is zero.
12.6.5.4 Transmit Underrun (TUR)
The transmit underrun bit is be set if the transmit FIFO experiences an underrun. When the UDC
experiences an underrun, UDCCSx[TUR] generates an interrupt. UDCCSx[TUR] is cleared by
writing a 1 to it.
12.6.5.5 Bit 4 Reserved
Bit 4 is reserved for future use.
12.6.5.6 Bit 5 Reserved
Bit 5 is reserved for future use.
12.6.5.7 Bit 6 Reserved
Bit 6 is reserved for future use.
12.6.5.8 Transmit Short Packet (TSP)
Software uses the transmit short packet to indicate that the last byte of a data transfer has been sent
to the FIFO. This indicates to the UDC that a short packet or zero-sized packet is ready to transmit.
Software must not set this bit if a packet of 256 bytes is to be transmitted. When the data packet is
successfully transmitted, this bit is cleared by the UDC.