7 line control register (lcr) – Intel PXA26X User Manual
Page 380
10-14
Intel® PXA26x Processor Family Developer’s Manual
Universal Asynchronous Receiver/Transmitter
10.4.2.7
Line Control Register (LCR)
The LCR specifies the format for the asynchronous data communications exchange. The serial data
format consists of a start bit, five to eight data bits, an optional parity bit, and one, one and a half,
or two stop bits. The LCR has bits that allow access to the divisor latch and bits that can cause a
break condition.
Table 10-12. Line Control Register
–
LCR (Sheet 1 of 2)
Base+0x0C
Line Control Register
UART
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
eser
ved
DL
A
B
SB
STKY
P
EPS
PEN
STB
WLS
1
WLS
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
Bits
Name
Description
31:8
—
Reserved
7
DLAB
DIVISOR LATCH ACCESS BIT:
Must be set high (logic 1) to access the Divisor Latches of the Baud Rate Generator during
a READ or WRITE operation. Must be set low (logic 0) to access the Receiver Buffer, the
Transmit Holding Register, or the IER.
0 – Access Transmit Holding register (THR), Receive Buffer register (RBR) and IER.
1 – Access Divisor Latch registers (DLL and DLH)
6
SB
SET BREAK:
Causes a break condition to be transmitted to the receiving UART. Acts only on the TXD
pin and has no effect on the transmitter logic. In FIFO mode, wait until the transmitter is
idle, LSR[TEMT]=1, to set and clear SB.
0 – No effect on TXD output
1 – Forces TXD output to 0 (space)
5
STKYP
STICKY PARITY:
Forces the bit value at the parity bit location to be the opposite of the EPS bit, rather than
the parity value. This stops parity generation. If PEN = 0, STKYP is ignored.
0 – No effect on parity bit
1 – Forces parity bit to be opposite of EPS bit value
4
EPS
EVEN PARITY SELECT:
Even parity select bit. If PEN = 0, EPS is ignored.
0 – Sends or checks for odd parity
1 – Sends or checks for even parity