Intel PXA26X - Manual (Page 59)

Intel® PXA26x Processor Family Developer’s Manual 2-29
System Architecture
0x4090 000C RTTR RTC Timer Trim Register
OS Timer 0x40A0 0000
0x40A0 0000 OSMR<0>
OS Timer Match Registers<3:0>
0x40A0 0004 OSMR<1>
0x40A0 0008 OSMR<2>
0x40A0 000C OSMR<3>
0x40A0 0010 OSCR OS Timer Counter Register
0x40A0 0014 OSSR OS Timer Status Register
0x40A0 0018 OWER OS Timer Watchdog Enable Register
0x40A0 001C OIER OS Timer Interrupt Enable Register
PWM 0 0x40B0 0000
0x40B0 0000 PWM_CTRL0 PWM 0 Control Register
0x40B0 0004 PWM_PWDUTY0 PWM 0 Duty Cycle Register
0x40B0 0008 PWM_PERVAL0 PWM 0 Period Control Register
PWM 1 0x40C0 0000
0x40C0 0000 PWM_CTRL1 PWM 1Control Register
0x40C0 0004 PWM_PWDUTY1 PWM 1 Duty Cycle Register
0x40C0 0008 PWM_PERVAL1 PWM 1 Period Control Register
Interrupt
Control
0x40D0 0000
0x40D0 0000 ICIP Interrupt Controller IRQ Pending Register
0x40D0 0004 ICMR Interrupt Controller Mask Register
0x40D0 0008 ICLR Interrupt Controller Level Register
0x40D0 000C ICFP Interrupt Controller FIQ Pending Register
0x40D0 0010 ICPR Interrupt Controller Pending Register
0x40D0 0014 ICCR Interrupt Controller Control Register
GPIO 0x40E0 0000
0x40E0 0000 GPLR0 GPIO Pin-Level Register GPIO<31:0>
0x40E0 0004 GPLR1 GPIO Pin-Level Register GPIO<63:32>
0x40E0 0008 GPLR2 GPIO Pin-Level Register GPIO<80:64>
0x40E0 000C GPDR0 GPIO Pin Direction Register GPIO<31:0>
0x40E0 0010 GPDR1 GPIO Pin Direction Register GPIO<63:32>
0x40E0 0014 GPDR2 GPIO Pin Direction Register GPIO<80:64>
0x40E0 0018 GPSR0 GPIO Pin Direction Register GPIO<31:0>
0x40E0 001C GPSR1 GPIO Pin Output Set Register GPIO<63:32>
0x40E0 0020 GPSR2 GPIO Pin Output Set Register GPIO<80:64>
0x40E0 0024 GPCR0 GPIO Pin Output Clear Register GPIO<31:0>
0x40E0 0028 GPCR1 GPIO Pin Output Clear Register GPIO <63:32>
0x40E0 002C GPCR2 GPIO Pin Output Clear Register GPIO <80:64>
0x40E0 0030 GRER0 GPIO Rising-Edge Detect Register GPIO<31:0>
0x40E0 0034 GRER1 GPIO Rising-Edge Detect Register GPIO<63:32>
Table 2-8. Register Address Summary (Sheet 9 of 13)
Unit Address Register Symbol Register Description