Intel PXA26X User Manual
Page 19
Intel® PXA26x Processor Family Developer’s Manual
xix
Contents
6-33
Common Memory Space Read Commands ............................................................................6-63
6-34
Attribute Memory Space Write Commands .............................................................................6-63
6-35
Attribute Memory Space Read Commands .............................................................................6-63
6-36
16-Bit I/O Space Write Commands (nIOIS16 = 0) ...................................................................6-63
6-37
16-Bit I/O Space Read Commands (nIOIS16 = 0)...................................................................6-63
6-38
8-Bit I/O Space Write Commands (nIOIS16 = 1) .....................................................................6-64
6-39
8-Bit I/O Space Read Commands (nIOIS16 = 1).....................................................................6-64
6-40
BOOT_DEF Register Bitmap...................................................................................................6-72
6-41
Memory Controller Pin Reset Values.......................................................................................6-76
7-1
Pin Descriptions.........................................................................................................................7-4
7-2
LCD Controller Control Register 0 ...........................................................................................7-20
7-3
LCD Controller Data Pin Utilization..........................................................................................7-26
7-4
LCD Controller Control Register 1 ...........................................................................................7-28
7-5
LCD Controller Control Register 2 ...........................................................................................7-31
7-6
LCD Controller Control Register 3 ...........................................................................................7-33
7-7
LCD DMA Frame Descriptor Address Registers .....................................................................7-38
7-8
LCD DMA Frame Source Address Registers ..........................................................................7-39
7-9
LCD Frame ID Registers .........................................................................................................7-39
7-10
LCD DMA Command Registers...............................................................................................7-40
7-11
LCD DMA Frame Branch Registers (FBRx) ............................................................................7-42
7-12
LCD Controller Status Register ...............................................................................................7-43
7-13
LCD Controller Interrupt ID Register........................................................................................7-46
7-14
TMED RGB Seed Register ......................................................................................................7-47
7-15
TMED Control Register............................................................................................................7-47
7-16
LCD Controller Register Locations ..........................................................................................7-49
8-1
External Interface to Codec .......................................................................................................8-1
8-2
SSP Control Register 0 (SSCR0) Bitmap and Bit Definitions ....................................................8-9
8-3
SSP Control Register 1 (SSCR1) Bitmap and Definitions .......................................................8-11
8-4
TFT and RFT Values for DMA Servicing .................................................................................8-15
8-5
SSP Data Register (SSDR) Bitmap and Definitions ................................................................8-16
8-6
SSP Status Register (SSSR) Bitmap and Bit Definitions.........................................................8-17
8-7
SSP Register Address Map .....................................................................................................8-19
9-1
MMC Signal Description ............................................................................................................9-1
9-2
I2C Bus Definitions ...................................................................................................................9-2
9-3
Modes of Operation ...................................................................................................................9-3
9-4
START and STOP Bit Definitions ..............................................................................................9-5
9-5
Master Transactions ................................................................................................................9-12
9-6
Slave Transactions ..................................................................................................................9-15
9-7
General Call Address Second Byte Definitions .......................................................................9-17
9-8
I
2
C Register Definitions ...........................................................................................................9-22
9-9
I2C Bus Monitor Register - IBMR ...........................................................................................9-23
9-10
I2C Data Buffer Register - IDBR.............................................................................................9-23
9-11
I2C Control Register - ICR......................................................................................................9-24
9-12
I2C Status Register - ISR .......................................................................................................9-27
9-13
I2C Slave Address Register - ISAR ........................................................................................9-28
10-1
UART Signal Descriptions .......................................................................................................10-3
10-2
UART Register Addresses as Offsets of a Base .....................................................................10-6
10-3
Receive Buffer Register – RBR ...............................................................................................10-6
10-4
Transmit Holding Register – THR............................................................................................10-7
10-5
Divisor Latch Low Register – DLL ...........................................................................................10-8