12 power manager register locations – Intel PXA26X User Manual
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Intel® PXA26x Processor Family Developer’s Manual
Clocks and Power Manager
3.5.12
Power Manager Register Locations
Table 3-20
shows the registers associated with the power manager and the physical addresses used
to access them.
.
Table 3-19. RCSR Bit Definitions
0x40F0_0030
RCSR
Clocks and Power Manager
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Re
s
e
rv
e
d
GP
R
SM
R
WD
R
HW
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
[31:4]
—
Reserved
3
GPR
GPIO RESET:
0 – GPIO reset has not occurred since the last time the CPU or hardware reset cleared
this bit.
1 – GPIO reset has occurred since the last time the CPU or hardware reset cleared this
bit.
Cleared by hardware reset and by setting to a 1.
2
SMR
SLEEP MODE:
0 – Sleep mode has not occurred since the last time the CPU or hardware reset cleared
this bit.
1 – Sleep mode has occurred since the last time the CPU or hardware reset cleared this
bit.
Cleared by hardware reset and by setting to a 1.
1
WDR
WATCHDOG RESET:
0 – Watchdog reset has not occurred since the last time the CPU or hardware reset
cleared this bit.
1 – Watchdog reset has occurred since the last time the CPU or hardware reset cleared
this bit.
Cleared by hardware reset and by setting to a 1.
0
HWR
HARDWARE RESET:
0 – Hardware reset has not occurred since the last time the CPU cleared this bit.
1 – Hardware reset has occurred since the last time the CPU cleared this bit.
Set by hardware reset. Cleared by setting to a 1.
Table 3-20. Power Manager Register Locations (Sheet 1 of 2)
Address
Name
Description
0x40F0 0000
PMCR
Power Manager Control Register
0x40F0 0004
PSSR
Power Manager Sleep Status Register
0x40F0 0008
PSPR
Power Manager Scratch Pad Register
0x40F0 000C
PWER
Power Manager Wake-up Enable Register
0x40F0 0010
PRER
Power Manager GPIO Rising-edge Detect Enable Register
0x40F0 0014
PFER
Power Manager GPIO Falling-edge Detect Enable Register
0x40F0 0018
PEDR
Power Manager GPIO Edge Detect Status Register